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smsc ds ? lan91c100fd rev. b rev. 01-20-06 lan91c100fd rev. b feast fast ethernet controller with full duplex capability features ? dual speed csma/cd engine (10 mbps and 100 mbps) ? compliant with ieee 802.3 100base-t specification ? supports 100base-tx, 100base-t4, and 10base-t physical interfaces ? 32 bit wide data path (i nto packet buffer memory) ? support for 32 and 16 bit buses ? support for 32, 16 and 8 bit cpu accesses ? synchronous, asynchronous and burst dma interface mode options ? 128 kbyte external memory ? built-in transparent arbitr ation for slave sequential access architecture ? early tx, early rx functions ? flat mmu architecture with symmetric transmit and receive structures and queues ? mii (media independent interface) compliant mac- phy interface running at nibble rate ? mii management serial interface ? seven wire interface to 10 mbps endec ? eeprom-based setup ? full duplex capability general description the lan91c100fd is designed to facilitat e the implementation of first generation fast ether net adapters and connectivity products. for this first generation of produc ts, flexibility dominates ov er integration. the lan 91c100fd is a digital device that implements the mac porti on of the csma/cd protocol at 10 and 100 mbps, and couples it with a lean and fast data and control path system architecture to ensure the cpu to packet ram data move ment does not cause a bottleneck at 100 mbps. total memory size is 128 kbytes, equivalent to a total chip storage (transmit plus receiv e) of 64 outstanding packets. the lan91c100fd is software compatible with the lan9000 fam ily of products and can use ex isting lan9000 drivers (odi, ipx, and ndis) in 16 and 32 bit intel x86 based environments. memory management is handled using a unique mmu (memory management unit) architecture and a 32-bit wide data path. this i/o mapped architecture can sustain back-to-back frame trans mission and reception for superior data throughput and optimal performance. it also dynamically allocates buffer memory in an efficient buffer utilization scheme, reducing software tasks and relieving the host cp u from performing these hous ekeeping functions. the total memory size is 128 kbytes (external), equivalent to a total chip storage (transmi t and receive) of 64 outstanding packets. feast provides a flexible slave interface for easy connecti vity with industry-standard buses. the bus interface unit (biu) can handle synchronous as well as asynchronous bus es, with different signals being used for each one. feast's bus interface supports sync hronous buses like the vesa local bus, as well as burst mode dma for eisa environments. asynchronous bus support for isa is suppor ted even though isa cannot sust ain 100 mbps traffic. fast ethernet could be adopted fo r isa-based nodes on the basis of the aggregate traffic benefits. two different interfaces are supported on the network side. t he first is a conventional sev en wire endec interface that connects to the lan83c694 for 10base-t and coax 10 mbps et hernet networks. the second interface follows the mii (media independent interface) specif ication draft standard, consisti ng of 4 bit wide data transfers at the nibble rate. this interface is applicable to 10 mbps or 100 mbps networks. three of the lan91c100fd?s pins are used to interface to the two-line mii serial management protocol. four i/o ports (one input and three output pins ) are provided for lan83c694 configuration.
smsc ds ? lan91c100fd r ev. b page 2 rev. 01-20-06 the lan91c100fd is based on the lan91c100 feast, functional revision g modified to add full duplex capability. also added is a software-controlled option to allow collisions to di scard receive packets. previously, the lan91c100 supported a ?diagnostic full duplex? mode. under th is mode the transmit packet is looped inter nally and received by the mac. this mode was enabled using the fduplx bit in t he tcr. in order to avoid confusion, the new, broader full duplex function of the lan91c100fd is designated as switc hed full duplex, and the tcr bit enabling it is designated as swfdup. when the lan91c100fd is configured for swfdup, its transmit and receive pat hs will operate independently and some csma/cd functions will be disabled. w hen the controller is not configured for swfdup it will follow the csma/cd protocol. 80 arkay drive hauppauge, ny 11788 (631) 435-6000 fax (631) 273-3123 copyright ? 2006 smsc or its s ubsidiaries. all rights reserved. circuit diagrams and other information rela ting to smsc products are included as a m eans of illustrating typical applications. consequently, complete information sufficient for construction pur poses is not necessarily given. although the informat ion has been checked and is bel ieved to be accurate, no responsibility is assumed for ina ccuracies. smsc reserves the ri ght to make changes to specif ications and product descriptions at any time without notice. contact your local smsc sales office to obtain the late st specifications bef ore placing your product order. the provisi on of this information does not convey to the purchas er of the described semiconducto r devices any licenses under any patent rights or other intellect ual property rights of smsc or others. all sales are expressly conditional on your agr eement to the terms and conditions of the most re cently dated ve rsion of smsc's standard terms of sale agreement dated before the date of y our order (the "terms of sale ag reement"). the product may contain d esign defects or errors known as anomalies which may cause the product's f unctions to deviate from published s pecifications. a nomaly sheets are available upon request. smsc products are not des igned, intended, authorized or wa rranted for use in any life s upport or other application whe re product failure could cause or contri bute to personal injury or severe property damage. an y and all such uses without prior written approval of an officer of smsc and further testing and/or modification will be fully at the risk of the customer. copies of this document or other smsc litera ture, as well as the terms of sale agreement, may be obtained by visiting smsc?s website at http:// www.smsc.com. smsc is a registered tr ademark of standard microsystems corporation (?smsc?). product names and company names are the trademarks of their respective holders. smsc disclaims and excludes any and all warranties, including without limitation any and all implied warranties of merchantability, fitness for a particular purpose, ti tle, and against infringement and the like, and any and all warranties arising from any course of dealing or usag e of trade. in no event shall smsc be liable for any direct, incidental, indirect, special, p unitive, or consequential damages; or for lost data, profits, savings or revenues of any kind; regardless of the form of action, whether based on contract; tort; negligence of smsc or others; strict liability; breach of warranty; or othe rwise; whether or not any remedy of buyer is held to have failed of its essential purpose, and whether or no t smsc has been advised of the possibility of such damages. ordering information order numbers: lan91c100-fd for 208-pin qfp package lan91c100-fd-ss for 208-pin qfp package (green, lead-free) lan91c100-fd for 208-pin tqfp package LAN91C100-FD-ST for 208-pin tqfp package (green, lead-free)
smsc ds ? lan91c100fd r ev. b page 3 rev. 01-20-06 table of contents feature s....................................................................................................................... .........1 general des cription ........................................................................................................1 pin config uratio n.............................................................................................................. 4 description of pin funct ions .......................................................................................5 functional des cription ................................................................................................12 data structures and registers...............................................................................16 board setup info rmation ............................................................................................46 application cons ideratio ns .......................................................................................48 operational d escription .............................................................................................56 maximum guaranteed ratings*....................................................................................56 dc electrical characteris tics ..................................................................................56 timing di agram s ................................................................................................................ 59
smsc ds ? lan91c100fd r ev. b page 4 rev. 01-20-06 pin configuration lnk txen xtal1 xtal2 vdd miisel ncsout nrxdisc tx25 vdd rx_er rx_dv ios0 gnd ios1 ios2 rx25 col100 crs100 rxd0 rxd1 rxd2 vdd rxd3 txd0 txd1 vdd txd2 txd3 txen100 nrwe0 gnd rd7 rd6 rd5 rd4 rdmah rd3 rd2 rd1 vdd rd0 rd15 rd14 rd13 gnd rd12 rd11 rd10 gnd eneep eedo 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 d8 vdd d9 d10 d11 d12 gnd d13 d14 d15 gnd d16 vdd d17 d18 d19 gnd d20 d21 vdd d22 d23 gnd d24 gnd vdd d25 d26 gnd d27 d28 d29 d30 gnd d31 nrdyrtn nldev vdd nsrdy lclk 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 crs col rxd avdd nc agnd lbk txd gnd rxc mdi txc mdo nfstep auisel aen mclk vdd ndatacs intr3 intr2 intr1 vdd gnd w/nr ncycle reset nvlbus gnd vdd nwr nrd intr0 ardy gnd d0 d1 d2 d3 gnd d4 d5 d6 vdd d7 nbe3 nbe2 nbe1 nbe0 a15 a14 a13 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 lan91c100fd 208 pin pqfp and tqfp 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 eedi eesk eecs rd9 nrwe1 nc rd8 rd23 rd22 rd21 vdd rd20 rd19 gnd rd18 rd17 rd16 rd31 rd30 nc nrwe2 vdd gnd rd29 rd28 rd27 rd26 rd25 rd24 gnd vdd ra2 vdd nrwe3 ra3 ra4 ra12 ra5 ra6 ra13 rcvdma gnd nads ra7 nroe ra11 ra8 ra10 ra9 ra15 ra14 ra16
smsc ds ? lan91c100fd r ev. b page 5 rev. 01-20-06 description of pin functions pqfp/tqfp pin no. name symbol buffer type description 148-159 address a4-a15 i input. decoded by lan91c100fd to determine access to its registers. 145-147 address a1-a3 i input. used by lan91c100fd for internal register selection. 193 address enable aen i input. used as an address qualifier. address decoding is only enabled when aen is low. 160-163 nbyte enable nbe0- nbe3 i input. used during lan91c100fd register accesses to determine the width of the access and the register(s) being accessed. nbe0-nbe3 are ignored when ndatacs is low (burst accesses) because 32 bit transfers are assumed. 173-170, 168-166, 164, 144, 142-139, 137-135, 133, 131-129, 127, 126, 124, 123, 121, 118, 117, 115-112, 110 data bus d0-d31 i/o24 bidirectional. 32 bit data bus used to access the lan91c100fd?s internal registers. data bus has weak internal pullups. supports direct connection to the system bus without external buffering. for 16 bit systems, only d0-d15 are used. 182 reset reset is input. this input is not considered active unless it is active for at least 100ns to filter narrow glitches. 95 naddress strobe nads is input. for systems that require address latching, the rising edge of nads indicates the latching moment for a1-a15 and aen. all lan91c100fd internal functions of a1-a15, aen are latched except for nldev decoding. 183 ncycle ncycle i input. this active low signal is used to control lan91c100fd eisa burst mode synchronous bus cycles. 184 write/ nread w/nr is input. defines the direction of synchronous cycles. write cycles when high, read cycles when low. 181 nvl bus access nvlbus i with pullup input. when low, the lan91c100fd synchronous bus interface is configured for vl bus accesses. otherwise, the lan91c100fd is configured for eisa dma burst accesses. does not affect the asynchronous bus interface. 105 local bus clock lclk i input. used to interface synchronous buses. maximum frequency is 50 mhz. limited to 8.33 mhz for eisa dma burst mode. 175 asynchron- ous ready ardy od16 open drain output. ardy may be used when interfacing asynchronous buses to extend accesses. its rising (access completion) edge is controlled by the xtal1 clock and, therefore, asynchronous to the host cpu or bus clock. 106 nsynchron - ous ready nsrdy o16 output. this out put is used when interfacing synchronous buses and nvlbus=0 to extend accesses. this signal remains normally inactive, and its falling edge indicates completion. this signal is synchronous to the bus clock lclk.
smsc ds ? lan91c100fd r ev. b page 6 rev. 01-20-06 description of pin functions pqfp/tqfp pin no. name symbol buffer type description 109 nready return nrdyrtn i input. this input is used to complete synchronous read cycles. in eisa burst mode it is sampled on falling lclk edges, and synchronous cycles are delayed until it is sampled high. 176, 187-189 interrupt intr0- intr3 o24 outputs. only one of t hese interrupts is selected to be used; the other three are tri-stated. the selection is determined by the value of int sel 1- 0 bits in the configuration register. 108 nlocal device nldev o16 output. this active low output is asserted when aen is low and a4-a15 decode to the lan91c100fd address programmed into the high byte of the base address register. nldev is a combinatorial decode of unlatched address and aen signals. 177 nread strobe nrd is input. used in asynchronous bus interfaces. 178 nwrite strobe nwr is input. used in asynchronous bus interfaces. 190 ndata path chip select ndatacs i with pullup input. when ndatacs is low, the data path can be accessed regardless of the values of aen, a1- a15 and the content of the bank select register. ndatacs provides an interface for bursting to and from the lan91c100fd 32 bits at a time. 54 eeprom clock eesk o4 output. 4 sec clock used to shift data in and out of the serial eeprom. 55 eeprom select eecs o4 output. serial eepr om chip select. used for selection and command framing of the serial eeprom. 52 eeprom data out eedo o4 output. connected to the di input of the serial eeprom. 53 eeprom data in eedi i with pulldown input. connected to the do output of the serial eeprom. 13, 15, 16 i/o base ios0-ios2 i with pullup input. external switches can be connected to these lines to select between predefined eeprom configurations. 51 enable eeprom eneep i with pullup input. enables (when high or open) lan91c100fd accesses to the serial eeprom. must be grounded if no eeprom is connected to the lan91c100fd. 42, 40-38, 36-33 ram data bus rd0-rd7 i/o4 with pullups bidirectional. carries the local buffer memory read and write data. reads are always 32 bits wide. writes are controlled individua lly at the byte level. floated if fltst=1 during receive frame status word writes for packet forwarding information (ra2-ra16=0, rcvdma=1, nrwe0- nrwe3=0). 59, 56, 49-47, 45-43, 69-67, 65, 64, 62-60, 81-76, 71, 70 ram data bus rd8-rd31 i/o4 with pullups bidirectional. carries the local buffer memory read and write data. reads are always 32 bits wide. writes are controlled indivi dually at the byte level.
smsc ds ? lan91c100fd r ev. b page 7 rev. 01-20-06 description of pin functions pqfp/tqfp pin no. name symbol buffer type description 84, 87, 88, 90, 91, 96, 99, 101, 100, 98, 89, 92, 103, 102, 104 ram address bus ra2-ra16 o4 outputs. this bus specifies the buffer ram doubleword being accessed by the lan91c100fd. 97 nroe o4 output. active low signal used to read a doubleword from buffer ram. 31, 57, 73, 86 nrwe0- rwe3 o4 outputs. active low signals used to write any byte, word or dword in ram. 93 receive dma rcvdma o4 output. this pin is active during lan91c100fd write memory cycles of receive packets. 3 4 crystal 1 crystal 2 xtal1 xtal2 iclk an external 25 mhz crystal is connected across these pins. if a ttl clock is supplied instead, it should be connected to xtal1 and xtal2 should be left open. 5, 10, 23, 27, 41, 63, 74, 83, 85, 107, 119, 125, 132, 143, 165, 179, 186, 191 power vdd +5v power supply pins. 205 analog power avdd +5v analog power supply pins. 14, 32, 46, 50, 66, 75, 82, 94, 111, 116, 120, 122, 128, 134, 138, 169, 174, 180, 185, 200 ground gnd ground pins. 203 analog ground agnd analog ground pin. 2 transmit enable txen o4 output. used for 10 mbps endec. this pin stays low when miisel is high. 201 transmit data txd o4 output. nrz transmit data for 10 mbps endec interface. 208 carrier sense crs i with pulldown input. carrier sense from 10 mbps endec interface. this pin is ignored when miisel is high. 207 collision detect col i with pulldown input. collision detection indication from 10 mbps endec interface. this pin is ignored when miisel is high. 206 receive data rxd i with pullup input. nrz receive data from 10 mbps endec interface. this pin is ignored when miisel is high. 197 transmit clock txc i with pullup input. 10 mhz transmit clock used in 10 mbps operation. this pin is ignored when miisel is high. 199 receive clock rxc i with pullup input. 10 mhz receive clock recovered by the 10 mbps endec. this pin is ignored when miisel is high.
smsc ds ? lan91c100fd r ev. b page 8 rev. 01-20-06 description of pin functions pqfp/tqfp pin no. name symbol buffer type description 202 loopback lbk o4 output. active w hen loop bit is set (tcr bit 1). independent of port sele ction (miisel=x). 1 nlink status nlnk i with pullup input. general purpose i nput port used to convey link status (ephsr bi t 14). independent of port selection (miisel=x). 195 nfullstep nfstep o4 output. non vola tile output pin. driven by inverse of fullstep (config bit 10). independent of port selection (miisel=x). 6 mii select miisel o4 output. non volatile output pin. driven by mii select (config bit 15). high indicates the mii port is selected, low indicates the 10 mbps endec is selected. 194 aui select auisel o4 output. n on volatile output pin. driven by aui select (config bit 8). independent of port selection (miisel= x). 30 transmit enable 100 mbps txen100 o12 output to mii phy. envelope to 100 mbps transmission. this pin stays low if miisel is low. 19 carrier sense 100 mbps crs100 i with pulldown input from mii phy. envelope of packet reception used for deferral and backoff purposes. this pin is ignored when miisel is low. 12 receive data valid rx_dv i with pulldown input from mii phy. envelope of data valid reception. used for receiv e data framing. this pin is ignored when miisel is low. 18 collision detect 100 mbps col100 i with pulldown input from mii phy. collision detection input. this pin is ignored when miisel is low. 25, 26, 28, 29 transmit data txd0- txd3 o12 outputs. transmit data nibble to mii phy. 9 transmit clock tx25 i with pullup input. transmit clock input from mii. nibble rate clock (25 mhz). this pin is ignored when miisel is low. 17 receive clock rx25 i with pullup input. receive clock input from mii phy. nibble rate clock. this pin is ignored when miisel is low. 20, 21, 22, 24 receive data rxd0- rxd3 i inputs. received data nibble from mii phy. these pins are ignored when miisel is low. 198 manage- ment data input mdi i with pulldown mii management data input. 196 manage- ment data output mdo o4 mii management data output. 192 manage- ment clock mclk o4 mii management clock. 11 receive error rx_er i with pulldown input. indicates a code error detected by phy. used by the lan91c100fd to discard the packet being received. the error indication reported for this event is the same as a bad crc (receive status word bit 13). this pin is ignored when miisel is low.
smsc ds ? lan91c100fd r ev. b page 9 rev. 01-20-06 description of pin functions pqfp/tqfp pin no. name symbol buffer type description 7 nchip select output ncsout o4 output. chip select provided for mapping of phy functions into lan91c100fd decoded space. active on accesses to lan91c100fd?s eight lower addresses when the bank selected is 7. 8 nreceive packet discard nrxdisc i with pullup input. used to discard the receive packet being stored in memory. assertion of the pin during a packet reception results in the interruption of packet reception into memory. the memory allocated to the packet and the packet number in use are freed. the input is driven asynchronously and is synchronized internally by the lan91c100fd. pin assertion may take place at any time during the receive dma packet. the assertion has no effect if there is no packet being dmaed to memory or if asserted during the last dma write to memory. works for both mii and endec. the typical use of nrxdisc is with the lan91c100fd in prms mode with an external associative memory use for address filtering. *note: the pin must be asserted for a minimum of 80ns. 37 rdmah o4 output. active when the first dword of the address is written (rcvdma= 1, ra10-ra4=0, ra3- ra2=x). buffer types o4 output buffer with 2ma source and 4ma sink o12 output buffer with 6ma source and 12ma sink o16 output buffer with 8ma source and 16ma sink o24 output buffer with 12ma source and 24ma sink od16 open drain buffer with 16ma sink i/o4 bidirectional buffer with 2ma source and 4ma sink i/o24 bidirectional buffer with 12ma source and 24ma sink i input buffer with ttl levels is input buffer with schmitt trigger hysteresis iclk clock input buffer dc levels and conditions defined in the dc electrical characteristics section.
smsc ds ? lan91c100fd r ev. b page 10 rev. 01-20-06 table 1 - lan91c100fd pin requirements function pin symbols number of pins system address bus a1-a15, aen, nbe0-nbe3 20 system data bus d0-d31 32 system control bus reset, nads, lclk, ardy, nrdyrtn, nsrdy, intr0- intr3, nldev, nrd, nwr, ndatacs, ncycle, w/nr, nvlbus 17 serial eeprom eedi, eedo, eecs, eesk, eneep, ios0-ios2 8 ram data bus rd0-rd31 32 ram address bus ra2-ra16 15 ram control bus nroe, nrwe0-nrwe3, rcvdma, rdmah 7 crystal oscillator xtal1, xtal2 2 power vdd, avdd 19 ground gnd, agnd 21 external endec 10 mbps txen, txd, crs, col, rxd, txc, rxc, lbk, nlnk, nfstep, auisel, miisel 12 physical interface 100 m bps txen100, crs100, col100, rx_dv, rx_er, txd0-txd3, rxd0-rxd3, mdi, mdo, mclk 16 clocks tx25, rx25 2 miscellaneous ncsout, nrxdisc 2 total 205 figure 1 - lan91c100fd block diagram bus interface unit a rbiter memory management unit direct memory access media a ccess control seri a l eeprom rd fifo w r fifo address data control ram 25 mhz 10 mb interface 100 media independent interface
smsc ds ? lan91c100fd r ev. b page 11 rev. 01-20-06 figure 2 - lan91c100fd system diagram a ddress control data a ddress control data system bus serial eeprom 1o mbps mii rd0-31 oe,we ra sram 32kx8 1 2 3 4 lan91c100fd feast lan83c69 10base-t interface 10base-t 100base-t4 interface chip 100base-t4 100base-t x interface logic/ 10base-t 100base-tx/ 10base-t or
smsc ds ? lan91c100fd r ev. b page 12 rev. 01-20-06 functional description description of blocks clock generator block 1) the xtal1 and xtal2 pins are to be connected to a 25 mhz crystal. 2) txclk and rxclk are 10 mhz clock inputs. these clo cks are generated by the exter nal endec in 10 mbps mode and are only used by the csma/cd block. 3) tx25 is an input clock. it will be the nibble rate of the particular phy connect ed to the mii (2.5 mhz for a 10 mbps phy, and 25 mhz for a 100 mbps phy). 4) rx25 - this is the mii nibble rate receive clock used for sampling received data nibbles and running the receive state machine. (2.5 mhz for a 10 mbps phy, and 25 mhz for a 100 mbps phy). 5) lclk - bus clock - used by the biu for synchronous accesses. maximum frequency is 50 mhz for vl bus mode, and 8.33 mhz for eisa slave dma. csma/cd blockcsma/cd block this is a 16 bit oriented block, with fully- independent transmi t and receive logic. the data path in and out of the block consists of two 16-bit wide uni-directional fifos interfacing t he dma block. the dma port of the fifo stores 32 bits to exploit the 32 bit data path into memory, but the fifos themselves are 16 bit wide. the control path consists of a set of registers interfaced to the cpu via the biu. dma blockdma this block accesses packet memory on the csma/cd?s behalf, fetching transmit data and storing received data. it interfaces the csma/cd transmit and receive fifos on one si de, and the arbiter block on the other. to increase the bandwidth into memory, a 50 mhz clock is used by the dma block, and the dat a path is 32 bits wide. for example, during active reception at 100 mbps, the csma/cd block will write a word into the receive fifo every 160ns. the dma will read the fifo and accumulate two words on the output port to request a memory cycle from the arbiter every 320ns. dma will discard a packet if nrxdisc is asserted for a minimu m of 80ns during a reception. if asserted late, the dma will receive the packet normally. the nrxdisc is defined valid fo r the dma interface for as long as the rcvdma signal is active. the dma machine is able to support full duplex operation. independent receive and transmit counters are used. transmit and receive cycles are alternated when simu ltaneous receive and transmit accesses are needed. arbiter blockarbiter the arbiter block sequences accesses to packet ram reques ted by the biu and by the dma blocks. biu requests represent pipelined cpu accesses to the data register, while dma requests represent csma/cd data movement. the external memory used is a 25ns sram. the arbiter is also responsible for controlling the nrwe0- nrwe3 lines as a function of the bytes being written. read accesses are always 32 bit wide, and the ar biter steers the appropriate byte(s) to t he appropriate lanes as a function of the address. the cpu data path consists of two uni-directional fifos mapped at the data register location. these fifos can be accessed in any combination of bytes, word, or doublewords. the arbiter will indicate 'not ready' whenever a cycle is initiated that cannot be satisfied by the present state of the fifo.
smsc ds ? lan91c100fd r ev. b page 13 rev. 01-20-06 mmu blockmmu the hardware memory management unit allocates memory and transmit and receive packet queues. it also determines the value of the transmit and receive inte rrupts as a function of t he queues. the page size is 2k, with a maximum memory size of 128k. mir and mcr values are interpreted in 512 byte units. biu blockbiu the bus interface unit can handle synchronous as well as asynchronous buses; different signals are used for each one. transparent latches are added on the address path using rising nads for latching. when working with an asynchronous bus like isa, the read and writ e operations are controll ed by the edges of nrd and nwr. ardy is used for notifying the sy stem that it should ex tend the access cycle. the leading edge of ardy is generated by the leading edge of nrd or nwr while the trailing edge of ardy is c ontrolled by the internal lan91c100fd clock and, therefore, asynchronous to the bus. in the synchronous vl bus type mode, ncycle and lclk ar e used to for read and write oper ations. completion of the cycle may be determined by using nsrdy. nsrdy is controlled by lclk and synchronous to the bus. direct 32 bit access to the data path is supported by usi ng the ndatacs input. by asserting ndatacs, external dma type of devices will bypass the biu address decoders and can sequentially access memory with no cpu intervention. ndatacs accesses can be used in the eisa dma burst mode (n vlbus=1) or in asynchronous cycles. these cycles must be 32 bit cycles. please refer to the corres ponding timing diagrams for details on these cycles. the biu is implemented usi ng the following principles: 1) address decoding is based on t he values of a15-a4 and aen. 2) address latching is performed by using transparent latches that are tr ansparent when nads=0 and nrd=1, nwr=1 and latch on nads rising edge. 3) byte, word and doubleword accesses to all registers and data path are supported except a doubleword write to offset ch will only write the bank select register (offset fh). 4) no bus byte swapping is implemented (no eight bit mode). 5) word swapping as a function of a1 is implemented for 16 bit bus support. 6) the asynchronous interface uses nrd and nwr strobes. if necessary, a rdy is negated on the leading edge of the strobe. the ardy trailing edge is controlled by clk. 7) the vlbus synchronous interface uses lclk, nads, and w/nr as defined in the vesa specification as well as ncycle to control read and wr ite operations and generate nsrdy. 8) eisa burst dma cycles to and from the data regis ter are supported as defined in the eisa slave mode "c" specification when ndatacs is driven by ndak. 9) synchronous and asynchronous cycles can be mixed as long as they are not active simultaneously. 10) address and bank selection can be bypa ssed to generate 32 bit data path acce sses by activating the ndatacs pin. mac-phy interface blockmac-phy interface two separate interfaces are defined, one for the 10 mbps bit rate inte rface and one for the mii 100 mbps and 10 mbps nibble rate interface. the 10 mbps endec interface compri ses the signals used for interf acing ethernet endecs. the 100 mbps interface follows the mii for 100 mbps 802.3 networks proposal, and it is based on transferring nibbles between the mac and the phy. for the mii interface, transmit data is cl ocked out using the tx25 clock input, while receive data is clocked in using rx25. in 100 mbps mode, the lan91c100fd provides the following interface signals to the phy:
smsc ds ? lan91c100fd r ev. b page 14 rev. 01-20-06 ? for transmission: txen100 txd0-3 tx25 ? for reception: rx_d v rx_er rxd0-3 rx25 ? for csma/cd state machines: crs100 col100 a transmission begins by txen100 going active (high), and tx d0-txd3 having the first valid preamble nibble. txd0 carries the least significant bit of the nibble (that is the one that would go first out of the eph at 100 mbps), while txd3 carries the most significant bit of the nibble. txen100 and txd0-txd3 are clocked by the lan91c100fd using tx25 rising edges. txen100 goes inactive at the end of the packet on the last nibble of the crc. during a transmission, col100 might become active to i ndicate a collision. col100 is asynchronous to the lan91c100fd?s clocks and will be synchronized internally to tx25. reception begins when rx_dv (receive data valid) is asserted. a preamble pattern or flag octet will be present at rxd0- rxd3 when rx_dv is activated. the lan91c100fd requires no training sequence beyond a full flag octet for reception. rx_dv as well as rxd0-rxd3 are sampled on rx25 rising edges . rxd0 carries the least si gnificant bit and rxd3 the most significant bit of the nibble. rx _dv goes inactive when the last valid ni bble of the packet ( crc) is presented at rxd0-rxd3. rx_er might be asserted during packet reception to signal t he lan91c100fd that the present receive packet is invalid. the lan91c100fd will discard the packe t by treating it as a crc error. when miisel=1, rxd0-rxd3 should always be aligned to packet nibbles, therefore, opening flag detection does not consider misaligned cases. opening flag detection expects the 5dh pattern and w ill not reject the packet on non-preamble patterns. when miisel=0 the opening fl ag detection expects a "10101011" pattern and will use it for determining nibble alignment. crs100 is used as a frame envelope signal fo r the csma/cd mac state machines (def eral and backoff functions), but it is not used for receive framing functions. crs 100 is an asynchronous signal and it will be active whenever there is activity on the cable, including lan91c100f d transmissions and collisions. switching between the endec and mii inte rfaces is controlled by the mii sel ect bit in the config register. the miisel pin reflects the value of this bit and ma y be used to control external multiplexing logic. note that given the modul ar nature of the mii, tx25 and rx25 cannot be assumed to be free running clocks. the lan91c100fd will not rely on the presenc e of tx25 and rx25 during reset and will use its own internal clock whenever a timeout on tx25 is detected. mii management interface block phy management through the mii management interface is suppor ted by the lan91c100fd by providing the means to drive a tri-statable data out put, a clock, and reading an input. timing and fr aming for each management command is to be generated by the cpu. serial eeprom interface this block is responsible for reading the serial eepr om upon hardware reset (or equivalent command) and defining defaults for some key registers. a writ e operation is also implemented by this block, that under cp u command will program specific locations in the eeprom. this block is an autonomous state machine and cont rols the internal data bus of the lan91c100fd during active operation.
smsc ds ? lan91c100fd r ev. b page 15 rev. 01-20-06 figure 3 - lan91c100fd internal block diagram with data path bus interface arbiter mmu buffer ram csma/cd data bus address bus control eeprom eeprom write data reg read data reg tx fifo tx compl fifo rx fifo dma interface address data transmit receive
smsc ds ? lan91c100fd r ev. b page 16 rev. 01-20-06 data structures and registers packet format in buffer memory the packet format in memory is similar fo r the transmit and receive areas. the first word is reserved for the status word. the next word is used to specify the tota l number of bytes, and it is followed by the data area. t he data area holds the packet itself. figure 4 - data packet format transmit packet receive packet status word written by csma upon transmit completion (see status register) written by csma upon receive completion (see rx frame status word) byte count written by cpu written by csma data area written/modified by cpu written by csma control byte written by cpu to control odd/even data bytes written by csma; also has odd/even bit byte count - divided by two, it defines the total number of words including the status word, the byte count word, the data ar ea and the control byte. the receive byte count always appears as even; the oddfrm bit of the re ceive status word indicate s if the low byte of the last word is relevant. the transmit byte count least significant bit will be assumed 0 by the controller regardless of the value written in memory. data area - the data area starts at offset 4 of the packet structure and c an extend up to 2043 bytes. the data area contains six bytes of destination address followed by six bytes of source address, followed by a variable-length number of bytes. on transmit, all bytes ar e provided by the cpu, incl uding the source address. the lan91c100fd does not insert its own source address. on receive, all bytes are provided by the csma side. bit15 bit0 ram offset (decimal) 0 2 4 2046 max status word reserved byte count data area control byte last data byte if odd ~~ ~~ ~~ ~~
smsc ds ? lan91c100fd r ev. b page 17 rev. 01-20-06 the 802.3 frame length word (frame type in ethernet) is not interpreted by the lan91c100fd. it is treated transparently as data both for transmit and receive operations. control byte - for transmit packets the control byte is written by the cpu as: x x odd crc 0 0 0 0 odd - if set, indicates an odd number of bytes, with the la st byte being right before t he control byte. if clear, the number of data bytes is even and the byte bef ore the control byte is not transmitted. crc - when set, crc will be appended to the frame. this bit has only meaning if the nocrc bit in the tcr is set. for receive packets the control byte is written by the controller as: 0 1 odd 0 0 0 0 0 odd - if set, indicates an odd number of bytes, with the la st byte being right before t he control byte. if clear, the number of data bytes is even and the byte before the control byt e should be ignored. receive frame status wordreceive frame status word this word is written at the beginning of each receive frame in memory. it is not available as a register. high byte algn err brod cast bad crc odd frm toolng too short low byte hash value mult cast 5 4 3 2 1 0 algnerr - frame had alignment error. when mii sel=1 alignmet error is set when badcrc=1 and an odd number of nibbles was received between sfd and rx_dv going inactive . when mii sel=0 alignment error is set when badcrc=1 and the number of bits received between sfd and the crs going inactive is not an octet multiple. brodcast - receive frame was broadcast. badcrc - frame had crc error, or rx_e r was asserted during reception. oddfrm - this bit when set indicates that the received frame had an odd number of bytes. toolng - frame length was longer than 802.3 maximum size (1518 bytes on the cable). tooshort - frame length was shorter than 802. 3 minimum size (64 bytes on the cable).
smsc ds ? lan91c100fd r ev. b page 18 rev. 01-20-06 hash value - provides the hash value used to index the mult icast registers. can be used by receive routines to speed up the group address search. the hash val ue consists of the six most signific ant bits of the crc calculated on the destination address, and maps in to the 64 bit multicast table. bits 5,4,3 of the hash value se lect a byte of the multicast table, while bits 2,1,0 determine the bit within the byte selected. examples of the address mapping: address hash value 5-0 multicast table bit ed 00 00 00 00 00 0d 00 00 00 00 00 01 00 00 00 00 00 2f 00 00 00 00 00 000 000 010 000 100 111 111 111 mt-0 bit 0 mt-2 bit 0 mt-4 bit 7 mt-7 bit 7 multcast - receive frame was multicast. if hash value corres ponds to a multicast table bi t that is set, and the address was a multicast, the packet will pass address filter ing regardless of other filtering criteria. i/o space the base i/o space is determined by the ios0-ios2 input s and the eeprom contents. to limit the i/o space requirements to 16 locations, the registers are assigned to diffe rent banks. the last word of the i/o area is shared by all banks and can be used to change the bank in use. regist ers are described using t he following convention: offset name type symbol high byte bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 x x x x x x x x low byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x x x x x x x x offset - defines the address offset wi thin the iobase where the register can be accessed at, provided the bank select has the appropriate value. the offset specifies the address of the even byte (bits 0-7) or t he address of the complete word. the odd byte can be accessed using address (offset + 1). some registers (like the interrupt ack., or like interrupt mask) are functionally descr ibed as two eight bit registers, in that case the offset of each one is independently specified. regardless of the functional descripti on, all registers can be accessed as doublewords, words or bytes. the default bit values upon hard reset are highlighted below each register. table 2 - internal i/o space mapping bank0 bank1 bank2 bank3 0 tcr config mmu command mt0-1 2 eph status base pnr mt2-3 4 rcr ia0-1 fifo ports mt4-5 6 counter ia2-3 pointer mt6-7 8 mir ia4-5 data mgmt a mcr general data revision c reserved (0) control interrupt ercv e bank select bank select bank select bank select a special bank (bank7) exists to suppor t the addition of external registers.
smsc ds ? lan91c100fd r ev. b page 19 rev. 01-20-06 bank select register offset name type symbol e bank select register read/write bsr high byte 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 low byte bs2 bs1 bs0 x x x x x 0 0 0 bs2, bs1, bs0 determine the bank presently in use. this register is always accessible and is used to select the register bank in use. the upper byte always reads as 33h and can be used to help determine the i/o loca tion of the lan91c100fd. the bank select register is always accessible regardless of the value of bs0-2. note that the bank select regi ster can be accessed as a doublew ord at offset ch, as a word at offset eh, or as at offset fh, however a doubleword write to offset ch w ill write the bank select regis ter but will not write the registers ch and dh. bank 7 has no internal registers other than the bank select register itself. on valid cycles where bank7 is selected (bs0=bs1=bs2=1), and a3=0, ncsout is activated to facilitate implementation of external registers. note: bank7 does not exist in lan 91c9x devices. for backward s/w com patibility bank7 accesses should be done if the revision control register indi cates the device is the lan91c100fd. bank 0 offset name type symbol 0 transmit control register read/write tcr this register holds bits programmed by the cpu to control some of the protocol transmit options. high byte swfdup 0 eph loop stp sqet fduplx mon_ csn 0 nocrc 0 0 0 0 0 0 0 0 low byte pad_en 0 0 0 0 forcol loop txena 0 0 0 0 0 0 0 0 swfdup - enables switched full duplex mode. in this mode, transmit state machi ne is inhibited from recognizing carrier sense, so deferrals will not occur. also inhibits collision count, ther efore, the collision related st atus bits in the ephsr a re not valid (ctr_rol, latcol, sqet, 16col, mul col, and sngl col). uses col100 as flow control, limiting backoff and jam to 1 clock each before inter-frame gap, then retry will occur after ifg. if col100 is active during preamble, full preamble will be output before jam. when swfdup is high, the values of fduplx and mon_csn have no effect. this bit should be low for non-mii operation. eph_loop - internal loopback at the eph block. serial dat a is internally looped back when set. defaults low. when eph_loop is high the following transmit outputs are forced i nactive: txd0-txd3 = 0h, txen100 = txen = 0, txd = 1. the following and external inputs are blocked: crs=crs100=0, col=col100=0, rx_dv= rx_er=0.
smsc ds ? lan91c100fd r ev. b page 20 rev. 01-20-06 stp_sqet - stop transmission on sqet error. if set, stops and disables transmitter on sqe te st error. does not stop on sqet error and transmits next frame if clear. defaults low. fduplx - when set it enables full duplex operation. this will cause frames to be received if they pa ss the address filter regardless of the source for the frame. when clear the node will not re ceive a frame sourced by itself. mon_csn - when set the lan91c100fd monitors carrier while transmitting. it must see its ow n carrier by the end of the preamble. if it is not seen, or if carri er is lost during transmission, the trans mitter aborts the frame without crc and turns itself off and sets the lost carr bit in the ephsr. when this bit is clear the transmitter ignores its own carrier. defaults low. should be 0 for mii operation. nocrc - does not append crc to transmitted frames when set. allows software to insert the desired crc. defaults to zero, namely crc inserted. pad_en - when set, the lan91c100fd will pad transmit frames shorter than 64 bytes with 00. does not pad frames when reset forcol - when set, the forcol bit will force a collision by not deferring deliberately. this bit is set and cleared only by the cpu. when txena is enabled with no packets in t he queue and while the forcol bit is set, the lan91c100fd will transmit a preamble pattern the next time a carrier is s een on the line. if a packet is queued, a preamble and sfd will be transmitted. this bit defaults low to normal operation. note: the latcol bit in the ephsr, setting up as a result of forcol, will reset txena to 0. in order to forc e another collision, txena must be set to 1 again. loop - loopback. general purpose output port used to control t he lbk pin. typically used to put the phy chip in loopback mode. txena - transmit enabled when set. transmit is disabl ed if clear. when the bit is cleared the lan91c100fd will complete the current transmission befor e stopping. when stopping due to an error, this bit is automatically cleared. bank 0 offset name type symbol 2 eph status register read only ephsr this register stores t he status of the last transmitted fr ame. this register value, upon individual transmit packet completion , is stored as the first word in the memo ry area allocated to the packet. packet in terrupt processing should use the copy in memory as the register itself will be updated by subsequent packet transmissions. t he register can be used for real time values (like txena and link ok). if txena is cleared t he register holds the last packet completion status. high byte tx unrn link_ ok 0 ctr _rol exc _def lost carr latcol 0 0 -nlnk pin 0 0 0 0 0 0 low byte tx defr ltx brd sqet 16col ltx mult mul col sngl col tx_suc 0 0 0 0 0 0 0 0 txunrn - transmit under run. set if under run occurs, it also clears txena bit in tcr. cleared by setting txena high. this bit may only be set if early tx is being used. link_ok - general purpose input port driven by nlnk pin inverted. typically us ed for link test. a transition on the value of this bit generates an interrupt. ctr_rol - counter roll over. when set one or more 4 bi t counters have reached maximu m count (15). cleared by reading the ecr register.
smsc ds ? lan91c100fd r ev. b page 21 rev. 01-20-06 exc_def - excessive defe rral. when set last/ current transmit was deferr ed for more than 1518 * 2 byte times. cleared at the end of every packet sent. lost_carr - lost carrier sense. when set indicates that carri er sense was not present at end of preamble. valid only if mon_csn is enabled. this condition causes txena bit in tcr to be reset. cleared by setting txena bit in tcr. latcol - late collision detected on last transmit frame. if set a late collision wa s detected (later than 64 byte times into th e frame). when detected the transmitter jams and turns itself off clearing the txena bit in tcr. cleared by setting txena in tcr. tx_defr - transmit deferred. when set, ca rrier was detected during the first 6.4 s of the inter fram e gap. cleared at the end of every packet sent. ltx_brd - last transmit frame was a broadcast. set if frame wa s broadcast. cleared at the star t of every transmit frame. sqet - signal quality error test. in mii, sqet bit is al ways set after first transmit, except if swfdup=1. as a consequence, the stp_sqet bit in the tcr r egister cannot be set as it will always re sult in transmit fata l error. in non-mii systems, the transmitter opens a 1.6 s window 0.8 s after transmission is completed and the receiver returns inactive. during this window, the transmitter expects to see the sqet si gnal from the transceiver. the absence of this signal is a 'signal quality error' and is reported in th is status bit. transmission stops and eph int is set if stp_sqet is in the tcr is also set when sqet is set. this bit is cleared by setting txena high. 16col - 16 collisions reached. set when 16 collisions are det ected for a transmit frame. txena bit in tcr is reset. cleared when txena is set high. ltx_mult - last transmit frame was a multicast. set if fram e was a multicast. cleared at the start of every transmit frame. mulcol - multiple collision detected fo r the last transmit frame. set when more than one collision was experienced. cleared when tx_suc is high at t he end of the packet being sent. snglcol - single collision detected for t he last transmit frame. set when a collis ion is detected. cleared when tx_suc is high at the end of the packet being sent. tx_suc - last transmit was successful. set if transmit completes without a fatal error. this bit is cleared by the start of a new frame transmission or when txena is set high. fatal errors are: 16 collisions (1/2 duplex mode only) sqet fail and stp_sqet = 1 (1/2 duplex mode only) fifo underrun carrier lost and mon_csn = 1 (1/2 duplex mode only) late collision (1/2 duplex mode only)
smsc ds ? lan91c100fd r ev. b page 22 rev. 01-20-06 bank 0 offset name type symbol 4 receive control register read/write rcr high byte soft rst filt car abort_ enb 0 reserved reserved strip crc rxen 0 0 0 0 0 0 0 0 low byte reserved reserved reserved reserved reserved almul prms rx_ abort 0 0 0 0 0 0 0 0 soft_rst - software-activated reset. active high. initiated by writing this bit high and terminated by writing the bit low. the lan91c100fd?s configuration is not preserved except fo r configuration, base, and ia 0-ia5 registers. eeprom is not reloaded after software reset. filt_car - filter carrier. when set filters leading edge of ca rrier sense for 12 bit times (3 nibble times). otherwise recognizes a receive frame as soon as carrier sens e is active. (does not filter rx dv on mii!) abort_enb - enables abort of receive when collision occu rs. defaults low. when set, the lan91c100fd will automatically abort a packet being receiv ed when the appropriate collision input is activated (col100 for mii, col for non- mii). this bit has no effect if the swfdup bit in the tcr is set. strip_crc - when set it strips the crc on received frames . when clear the crc is stored in memory following the packet. defaults low. rxen - enables the receiver when set. if cleared, completes receiving current frame and t hen goes idle. defaults low on reset. almul - when set accepts all multicast frames (frames in whic h the first bit of da is '1'). when clear accepts only the multicast frames that match the mult icast table setting. defaults low. prms - promiscuous mode. when set receives all frames. does not receive its own transmission unless it is in full duplex! rx_abort - this bit is set if a receive frame was abort ed due to length longer than 2k bytes. the frame will not be received. the bit is cleared by reset or by the cpu writing it low. reserved - must be 0.
smsc ds ? lan91c100fd r ev. b page 23 rev. 01-20-06 bank 0 offset name type symbol 6 counter register read only ecr counts four parameters for mac statisti cs. when any counter reaches 15 an interr upt is issued. all counters are cleared when reading the register and do not wrap around beyond 15. high byte number of exc. deffered tx number of deffered tx 0 0 0 0 0 0 0 0 low byte multiple collision count single collision count 0 0 0 0 0 0 0 0 each four bit counter is incremented every time the corresponding event, as defined in the eph status register bit description, occurs. note that the c ounters can only increment onc e per enqueued transmit packet, never faster, limiting the rate of interrupts that can be generated by the counter s. for example if a packet is successfully transmitted after one collision the single collision count field is incremented by one. if a pa cket experiences between 2 to 16 collisions, the multiple collision count field is incremented by one. if a packet ex periences deferral the number of deferred tx field is incremented by one, even if the packet experienced multiple deferrals during its collision retries. the counter register facilitates main taining statistics in the auto rel ease mode where no transmit interrupts are generated on successful transmissions. reading the register in the transmit service routine will be enough to maintain statistics. bank 0 offset name type symbol 8 memory information register read only mir high byte free memory available (in bytes * 256 * m) 1 1 1 1 1 1 1 1 low byte memory size (in bytes *256 * m) 1 1 1 1 1 1 1 1 free memory available - this register can be read at any ti me to determine the amount of free memory. the register defaults to the memory size upon re set or upon the reset mmu command. memory size - this register can be r ead to determine the total memory size. all memory related information is represented in 256 * m byte units, where the multiplier m is determined by the mcr upper byte. these register default to ffh, which should be interpreted as 256.
smsc ds ? lan91c100fd r ev. b page 24 rev. 01-20-06 bank 0 offset name type symbol a memory configuration register lower byte - read/write upper byte - read only mcr high byte memory size multiplier 0 0 1 1 0 1 0 1 low byte memory reserved for transmit (in bytes * 256 * m) 0 0 0 0 0 0 0 0 memory reserved for transmit - programming this val ue allows the host cpu to reserve memory to be used later for transmit, limiting the amount of memory that receive packets can use. when programmed for zero, the memory allocation between transmit and receive is completely dynamic. when programmed for a non-zero value, the allocation is dynamic if the free memory exceeds t he programmed value, while receive a llocation requests are denied if the free memory is less or equal to the programmed value. this regist er defaults to zero upon reset. it is not affected by the reset mmu command. the value written to the mcr is a reserved memory spac e in addition to any memory currently in use. if the memory allocated for transmit plus the reserved space for tr ansmit is required to be const ant (rather than grow with transmit allocations) the cpu should updat e the value of this register afte r allocating or releasing memory. the contents of the mir as well as the low byte of the mcr ar e specified in units of 256 * m bytes, where m is the memory size multiplier. m=2 for the lan91c100fd. a value of 04h in the lower byte of the mcr is equal to one 2k page (4 * 256 *2 = 2k); since memory must be reserved in multiples of pages, bits 0 and 1 of the mcr should be written to 1 only when the entire memory is being reserved for tr ansmit (i.e., low byte of mcr = ffh). bank1 offset name type symbol 0 configuration register read/write cr the configuration register holds bits that define the adapter configuration and are not expec ted to change during run-time. this register is part of the eeprom saved setup. high byte mii select no wait full step 0 aui select 1 0 1 0 0 0 0 0 low byte 1 0 reserved int sel1 int sel0 1 0 1 1 0 0 0 1 mii select - used to select the network interface port. w hen set, the lan91c100fd will use its mii port and interface a phy device at the nibble rate. when clear, the lan91c100fd will use its 10 mbps endec interface. this bit drives the mii sel pin. switching between ports should be done with transmitte r and receiver disabled and no transmit/receive packets in progress. no wait - when set, does not request additional wait states. an ex ception to this are accesses to the data register if not ready for a transfer. when clear, negates iochrdy for two to three clocks on any cycle to the lan91c100fd.
smsc ds ? lan91c100fd rev. b rev. 01-20-06 full step - this bit is a general purpose output port. its invers e value drives pin nfstep and it is typically connected to sel pin of the lan83c694. it can be used to select the signaling mode for the au i or as a general purpose non-volatile configuration pin. defaults low. aui select - this bit is a general purpose output port. its value drives pin auisel and it is typically connected to mode1 pin of the lan83c694. it can be used to se lect aui vs. 10base-t, or as a general pur pose non-volatile conf iguration pin. defaults low. reserved - must be 0. int sel1-0 - used to select one out of four interr upt pins. the three unused in terrupts are tristated. int sel1 int sel0 interrupt pin used 0 0 1 1 0 1 0 1 intr0 intr1 intr2 intr3 bank 1 offset name type symbol 2 base address register read/write bar this register holds the i/o address dec ode option chosen for the lan91c100fd. it is part of the eeprom saved setup and is not usually modified during run-time. high byte a15 a14 a13 a9 a8 a7 a6 a5 0 0 0 1 1 0 0 0 low byte reserved 1 0 0 0 0 0 0 0 1 a15 - a13 and a9 - a5 - these bits are compared agains t the i/o address on the bus to determine the iobase for the lan91c100fd?s registers. the 64k i/o space is fully decoded by the lan91c 100fd down to a 16 location space, therefore the unspecif ied address lines a4, a10, a11 and a12 must be all zeros. all bits in this register are loaded from the serial eepr om. the i/o base decode defaults to 300h (namely, the high byte defaults to 18h). reserved - must be 0.
smsc ds ? lan91c100fd r ev. b page 26 rev. 01-20-06 bank 1 offset name type symbol 4 through 9 individual address registers read/write iar these registers are loaded starting at word location 20h of the eeprom upon hardware reset or eeprom reload. the registers can be modified by the softwar e driver, but a store operation will not modify the eeprom individual address contents. bit 0 of individual addr ess 0 register corresponds to the fi rst bit of the address on the cable. low byte address 0 0 0 0 0 0 0 0 0 high byte address 1 0 0 0 0 0 0 0 0 low byte address 2 0 0 0 0 0 0 0 0 high byte address 3 0 0 0 0 0 0 0 0 low byte address 4 0 0 0 0 0 0 0 0 high byte address 5 0 0 0 0 0 0 0 0 bank 1 offset name type symbol a general purpose register read/write gpr high byte high data byte 0 0 0 0 0 0 0 0 low byte low data byte 0 0 0 0 0 0 0 0 this register can be used as a way of storing and retrieving non-volatile info rmation in the eeprom to be used by the software driver. the storage is word ori ented, and the eeprom word address to be r ead or written is s pecified using the six lowest bits of the pointer register. this register can also be used to s equentially program the indivi dual address area of the eeprom, that is normally protected from accident al store operations. this register will be used for eeprom read and write only when the eeprom select bit in the control register is set. this allows generic eeprom read and write routines that do not affect the basic setup of the lan91c100fd.
smsc ds ? lan91c100fd r ev. b page 27 rev. 01-20-06 bank 1 offset name type symbol c control register read/write ctr high byte 0 rcv_ bad 0 1 auto releas e 0 1 0 0 0 0 1 0 0 1 0 low byte le enable cr enable te enable 1 0 eeprom select reload store 0 0 0 1 0 0 0 0 rcv_bad - when set, bad crc packets are received. when clear bad crc packets do not generate interrupts and their memory is released. note: nrxdisc, when asserted, ove rrides rcv_bad. also, rcv_ bad does not modify the function of rcv discard in the early receive register. auto release - when set, transmit pages are released by tr ansmit completion if the transmission was successful (when tx_suc is set). in that case there is no status word a ssociated with its packet number, and successful packet numbers are not even written into the tx complet ion fifo. a sequence of transmit packets will generate an interrupt only when the sequence is completely transmitted (tx empty int will be se t), or when a packet in the sequence experiences a fatal error (tx int will be set). upon a fatal error txena is cleared and the transmission s equence stops. the packet number that failed, is present in the fifo ports register, and it s pages are not released, allo wing the cpu to restart the sequence after corrective action is taken. le enable - link error enable. when set it enables the link _ok bit transition as one of t he interrupts merged into the eph int bit. clearing the le enable bit after an eph int in terrupt, caused by a link_ok transition, will acknowledge the interrupt. le enable defaults low (disabled). cr enable - counter roll over enable. when set, it enables t he ctr_rol bit as one of the interrupts merged into the eph int bit. reading the counter register after an eph int in terrupt caused by a counter rollover, will acknowledge the interrupt. cr enable defaults low (disabled). te enable - transmit error enable. when set it enables transmi t error as one of the interrupts merged into the eph int bit. an eph int interrupt caused by a transmitter error is ack nowledged by setting txena bit in the tcr register to 1 or by clearing the te enable bit. te enable defaults low (disabled) . transmit error is any condition that clears txena with tx_suc staying low as described in the ephsr register. eeprom select - this bit allows the cpu to specify whic h registers the eeprom reload or store refers to. when high, the general purpose regist er is the only register read or written. when low, reload reads configuration, base and individual address, and store writes t he configuration and base registers. reload - when set it will read the eepr om and update relevant registers with its contents. clear s upon completing the operation. store - when set, stores the contents of all relevant registers in the serial eeprom. clears upon completing the operation. note: when an eeprom access is in progress the store and relo ad bits will be read back as high. the remaining 14 bits of this register will be invalid. during this time atte mpted read/write operat ions, other than polli ng the eeprom status, will not have any effect on the internal registers. the cpu can resume accesses to the lan91c100fd after both bits are low. a worst case reload operation initiat ed by reset or by software takes less than 750 s.
smsc ds ? lan91c100fd r ev. b page 28 rev. 01-20-06 bank2 offset name type symbol 0 mmu command register write only busy bit readable mmucr this register is used by the cpu to control the memory allocation, de-alloca tion, tx fifo and rx fifo control. the three command bits determine the command issued as described below: high byte low byte command 0 0 n2 n1 n0/busy x y z 0 command set: xyz 000 0) noop - no operation 001 1) allocate memory for tx - n2,n1,n0 defines the amount of memory reques ted as (value + 1) * 256 bytes. namely n2,n1,n0 = 1 will request 2 * 256 = 512 bytes. a shift-based divide by 256 of the packet length yields the appropriate value to be used as n2,n 1,n0. immediately generates a completion code at the allocation result register. can optionally generate an interrupt on successful completion. n2,n1,n0 are ignored by the la n91c100fd but should be implemented in lan91c100fd software drivers for lan9000 compatibility. 010 2) reset mmu to initial state - frees all memory allocations, clears relevant interrupts, resets packet fifo pointers. 011 3) remove frame from top of rx fifo - to be i ssued after cpu has complet ed processing of present receive frame. this command removes the receive pa cket number from the rx fifo and brings the next receive frame (if any) to the rx area (output of rx fifo). 100 4) remove and release top of rx fifo - like 3) but also releases all memory used by the packet presently at the rx fifo out put. the mmu busy time after issuing remove and release command depends on the time when the busy bit is cleared. the time from issuing remove and release command on the last receive packet to the time when receive fifo is empty depends on rx int bit turning low. an alternate approach can be c hecking the read rx fifo register. 101 5) release specific packet - frees all pages alloca ted to the packet specified in the packet number register. should not be used for frames pending trans mission. typically used to remove transmitted frames, after reading their completion status. can be us ed following 3) to release receive packet memory in a more flexible way than 4). 110 6) enqueue packet number into tx fifo - this is the normal method of transmitting a packet just loaded into ram. the packet number to be enqueued is taken from the packet number register. 111 7) reset tx fifos - this command will reset both tx fifos: the tx fifo holding the packet numbers awaiting transmission and the tx completion fifo. this command provides a mechanism for canceling packet transmissions, and reordering or by passing the transmit queue. the reset tx fifos command should only be used when the transmitter is disabled. unlike the reset mmu command, the reset tx fifos does not release any memory. note 1: bits n2,n1,n0 bits are ignored by the lan91c100fd but should be used for command 0 to preserve software compatibility with the lan91c92 and future devices . they should be zero for all other commands.
smsc ds ? lan91c100fd r ev. b page 29 rev. 01-20-06 note 2: when using the reset tx fifos command, the cpu is responsible for releasing the memory associated with outstanding packets, or re-enqueuing them. packet numbers in the completion fifo can be read via the fifo ports register before issuing the command. note 3: mmu commands releasing memory (commands 4 and 5) should only be issued if the corresponding packet number has memory allocated to it. command sequencing a second allocate command (command 1) should not be iss ued until the present one has co mpleted. completion is determined by reading the failed bit of the allocation result register or through the allocation interrupt. a second release command (commands 4, 5) should not be issued if the previous one is still being processed. the busy bit indicates that a release command is in progress. afte r issuing command 5, the cont ents of the pnr should not be changed until busy goes low. after issuing command 4, command 3 should not be issued until busy goes low. busy bit - readable at bit 0 of the mmu command register address. when set indi cates that mmu is still processing a release command. when clear, mmu has already completed last release command. busy and failed bits are set upon the trailing edge of command. bank 2 offset name type symbol 2 packet number register read/write pnr 0 0 packet number at tx area 0 0 0 0 0 0 0 0 packet number at tx area - the value written into this register determines which packet number is accessible through the tx area. some mmu commands use the number stored in th is register as the packe t number parameter. this register is cleared by a reset or a reset mmu command. offset name type symbol 3 allocation result register read only arr this register is updated upon an a llocate memory mmu command. failed 0 allocated packet number 1 0 0 0 0 0 0 0 failed - a zero indicates a successful allocation completion. if the allocation fails the bit is set and only cleared when the pending allocation is satisfied. defaults high upon reset and reset mmu command. for polling purposes, the alloc_int in the interrupt status register should be used because it is synchroni zed to the read oper ation. sequence: 1) allocate command 2) poll alloc_int bit until set 3) read allocation result register allocated packet number - packet number associated with the last memory allocation request. the value is only valid if the failed bit is clear. note: for software compatibility with future versions, the value read from the arr after an allocation request is intended to be written into the pnr as is, without masking higher bits (provided failed = 0).
smsc ds ? lan91c100fd r ev. b page 30 rev. 01-20-06 bank 2 offset name type symbol 4 fifo ports register read only fifo this register provides access to t he read ports of the receive fifo and the transmit completion fifo. the packet numbers to be processed by the interrupt serv ice routines are read from this register. high byte rempty 0 rx fifo packet number 1 0 0 0 0 0 0 0 low byte tempty 0 tx done packet number 1 0 0 0 0 0 0 0 rempty - no receive packets queued in the rx fifo. for polli ng purposes, uses the rcv_int bi t in the interrupt status register. top of rx fifo packet number - packet number presently at the output of the rx fifo. only valid if rempty is clear. the packet is removed from the rx fifo using mmu commands 3) or 4). tempty - no transmit packets in completion queue. for polling purposes, uses the tx_int bi t in the interrupt status register. tx done packet number - packet number pr esently at the output of the tx completion fifo. only valid if tempty is clear. the packet is removed when a tx int acknowledge is issued. note: for software compatibility with future versions, the value read from each fifo register is intended to be written into the pnr as is, without masking higher bits (p rovided tempty and rempty = 0 respectively). bank 2 offset name type symbol 6 pointer register read/write not empty is a read only bit ptr high byte rcv auto incr. read eten not empty pointer high 0 0 0 0 0 0 0 0 low byte pointer low 0 0 0 0 0 0 0 0 pointer register - the value of this register determines the address to be accessed within the transmit or receive areas. it will auto-increment on accesses to the data register when auto incr. is set. the increment is by one for every byte access, by two for every word access, and by four for every double word access. when rcv is set the address refers to the receive area and uses t he output of rx fifo as the packet number, w hen rcv is clear the address refers to the transmit area and uses the packet number at the packet number register. read - determines the type of access to follow. if the read bi t is high the operation intended is a read. if the read bit is low the operation is a write. loading a new pointer value, with the read bi t high, generates a pre-fetch into the data register for read purposes.
smsc ds ? lan91c100fd r ev. b page 31 rev. 01-20-06 readback of the pointer will indicate the value of the address last accessed by t he cpu (rather than t he last pre-fetched). this allows any interrupt routine that uses the pointer, to save it and restor e it without affect ing the process being interrupted. the pointer register should not be loaded until the data register fifo is empty. the not empty bit of this regis ter can be read to determine if the fi fo is empty. on reads, if iochrdy is not c onnected to the host, the da ta register should not be read before 370ns after the pointer was loaded to allow the data register fifo to fill. if the pointer is loaded using 8 bit writes, the lo w byte should be loaded first and the high byte last. eten - when set enables early transmit underrun detection. normal operation when clear. not empty - when set indicates that the write data fifo is not empty yet. the cpu can veri fy that the fifo is empty before loading a new pointer value. this is a read only bit. note: if auto incr. is not set, the pointer must be loaded with a dword aligned value. bank 2 offset name type symbol 8 through bh data register read/write data data high x x x x x x x x data low x x x x x x x x data register - used to read or write the data buffer by te/word presently addressed by the pointer register. this register is mapped into two uni-directional fifos that allow moving words to and from the lan91c100fd regardless of whether the pointer address is even, odd or dword aligned. data goes thr ough the write fifo into memory, and is pre- fetched from memory into the read fifo. if byte accesses are used, the appropriate (next) byte can be accessed through the data low or data high registers. t he order to and from the fifo is preser ved. byte, word and dword accesses can be mixed on the fly in any order. this register is mapped into two consec utive word locations to facilitate double word move operations regardless of the actual bus width (16 or 32 bits). the data register is accessible at any addr ess in the 8 through ah range, while the number of bytes being transferred is determined by a1 and nbe0-nbe3. the fifos are 12 bytes each. bank 2 offset name type symbol c interrupt status register read only ist rx_disc int ercv int eph int rx_ovrn int alloc int tx empty int tx int rcv int 0 0 0 0 0 1 0 0
smsc ds ? lan91c100fd r ev. b page 32 rev. 01-20-06 offset name type symbol c interrupt acknowledge register write only ack rx_disc int ercv int rx_ovrn int tx empty int tx int offset name type symbol d interrupt mask register read/write msk rx_disc int ercv int eph int rx_ovrn int alloc int tx empty int tx int rcv int 0 0 0 0 0 0 0 0 this register can be read and written as a word or as two individual bytes. the interrupt mask register bits enable the appropriate bi ts when high and disable them when low. an enabled bit being set will cause a hardware interrupt. eph int - set when the ethernet protocol handler section indicates one out of vari ous possible special conditions. this bit merges exception type of interrupt sources, whose service time is not critical to the execution speed of the low level drivers. the exact nature of the interr upt can be obtained from the eph status register (ephsr), and enabling of these sources can be done via the control register . the possible sources are: link - link test transition ctr_rol - statistics counter roll over txena cleared - a fatal transmit error occurred forcing txena to be cleared. tx_suc will be low and the specific reason will be reflected by the bits: ? txunrn - transmit underrun ? sqet - sqe error ? lost carr - lost carrier ? latcol - late collision ? 16col - 16 collisions rx_disc int - set when the nrxdisc pin counter in the ercv register increments to a value of ff. the rx_disc int bit latches the condition for the purpose of being polled or generating an interrupt, and will only be cleared by writing t he acknowledge register with the rx_disc int bit set. rx_ovrn int - set when 1) the receiver aborts due to an ove rrun due to a failed memory allocation, 2) the receiver aborts due to a packet length of greater t han 2k bytes, or 3) the receiver aborts due to the rcv discrd bit in the ercv register set. the rx_ovrn int bit latches the condition fo r the purpose of being polled or generating an interrupt, and will only be cleared by writing the acknowledge r egister with the rx_ovrn int bit set. alloc int - set when an mmu request for tx pages allocation is co mpleted. this bit is the complement of the failed bit in the allocation result register. the alloc int enable bit should only be set following an allocation command, and cleared upon servicing the interrupt. tx empty int - set if the tx fifo goes empty, can be us ed to generate a single interrupt at the end of a sequence of packets enqueued for transmission. this bit latches the empty c ondition, and the bit will stay se t until it is specifically cleared by writing the acknowledge register with the tx empty int bit set. if a real time reading of the fifo empty is desired, the bit should be first cleared and then read.
smsc ds ? lan91c100fd r ev. b page 33 rev. 01-20-06 the tx empty int enable should only be set after the following steps: a) a packet is enqueued for transmission b) the previous empty condi tion is cleared (acknowledged) tx int - set when at least one packet transmission was comp leted. the first packet number to be serviced can be read from the fifo ports register. the tx int bit is always t he logic complement of the tempty bit in the fifo ports register. after servicing a packet number, its tx int interrupt is removed by writing the interr upt acknowledge register with the tx int bit set. rcv int - set when a receive interrupt is generated. the fi rst packet number to be serviced can be read from the fifo ports register. the rcv int bit is always the logic comp lement of the rempty bit in the fifo ports register. ercv int - early receive interrupt. set whenever a receiv e packet is being received, and the number of bytes received into memory exceeds the value programmed as ercv t hreshold (bank 3, offset ch). ercv int stays set until acknowledged by writing the interrupt acknowledge register with the ercv int bit set. note: if the driver uses auto release mode it should enable tx empty int as well as tx int. tx empty int will be set when the complete sequence of packets is transmitted. tx int will be set if the sequence stops due to a fatal error on any of the packets in the sequence. figure 5 - interrupt structure 5 4 3 2 1 0 5 4 3 2 1 0 i n t e r r u p t s t a t u s r e g i s t e r i n t e r r u p t m a s k r e g i s t e r o e n o e n r d i s t 1 6 d a t a b u s d 0 - 7 d 8 - 1 5 e d g e d e t e c t or o n l i n k e r r l e m a s k c t r - r o l c r m a s k t e m a s k t x e n a t x _ s v c e p h s r i n t e r r u p t s m e r g e d i n t o e p h i n t d 2 d 4 d s q n q t x f i f o e m p t y n w r a c k d s q n q r x _ o v r n ( e p h s r ) a l l o c a t i on f a i l e d t x c o m p l e t i o n f i f o n o t e m p t y r c v f i f o n o t e m p t y r c v i n t t x i n t t x e m p t y i n t a l l o c i n t r x _ o v r n i n t e p h i n t i n t m a i n i n t e r r u p t s e r c v i n t 6 6
smsc ds ? lan91c100fd r ev. b page 34 rev. 01-20-06 bank3 offset name type symbol 0 through 7 multicast table read/write mt low byte multicast table 0 0 0 0 0 0 0 0 0 high byte multicast table 1 0 0 0 0 0 0 0 0 low byte multicast table 2 0 0 0 0 0 0 0 0 high byte multicast table 3 0 0 0 0 0 0 0 0 low byte multicast table 4 0 0 0 0 0 0 0 0 high byte multicast table 5 0 0 0 0 0 0 0 0 low byte multicast table 6 0 0 0 0 0 0 0 0 high byte multicast table 7 0 0 0 0 0 0 0 0 the 64 bit multicast table is used for group address filtering. the hash va lue is defined as the six mo st significant bits of t he crc of the destination addresses. the thr ee msb's determine the register to be used (mt0-mt7), while the other three determine the bit within the register. if the appropriate bit in the table is set, the packet is received. if the almul bit in the rcr register is set, all multicast addr esses are received regardless of the multicast table values. hashing is only a partial group addressing f iltering scheme, but being the hash value available as part of the receive status word, the receive routine can reduce the s earch time significantly. with the proper memory structure, t he search is limited to comparing only the multicast addresses t hat have the actual has h value in question.
smsc ds ? lan91c100fd r ev. b page 35 rev. 01-20-06 bank 3 offset name type symbol 8 management interface read/write mgmt high byte fltst msk_ crs100 0 0 1 1 0 0 1 1 low byte mdoe mclk mdi mdo 0 0 1 1 0 0 mdi pin 0 fltst - facilitates the inclusion of packet forwarding informa tion on the receive packet memory structure. when 0, rd0- rd7 is always driven. when 1, rd0 -rd7 is floated during receive frame status word writes (ra2-ra16=0, rcvdma=1, nrwe0-nrwe3=0). msk_crs100 - disables crs100 detection during tr ansmit in half duplex mode (swfdup=0). mdo - mii management output. the value of this bit drives the mdo pin. mdi - mii management input. the value of the mdi pin is readable using this bit. mdclk - mii management clock. the value of this bit drives the mdclk pin. mdoe - mii management output enable. when high pin md o is driven, when low pin mdo is tri-stated. the purpose of this interface, along wi th the corresponding pins is to impl ement mii phy management in software. bank 3 offset name type symbol a revision register read only rev high byte 0 0 1 1 0 0 1 1 low byte chip rev 1 0 0 0 0 0 0 0 chip - chip id. can be used by software drivers to identif y the device used. rev - revision id. incremented for each revision of a given device. offset name type symbol c early rcv register read/write ercv high byte nrxdisc pin counter 0 0 0 0 0 0 0 0 low byte rcv discrd 0 0 ercv threshold 0 0 0 1 1 1 1 1
smsc ds ? lan91c100fd r ev. b page 36 rev. 01-20-06 nrxdisc pin counter - 8-bit counter increments when a packet is discarded due to the nrxdisc pin being active. this counter will be reset to 00 when read. a count of ff w ill set the rx_disc int. the count will wrap around to 00 after ff. rcv discrd - set to discard a packet being received. will di scard packets only in the process of being received. when set prior to the end of receive packet, bit 4 (rxovrn) of the interrupt st atus register will be set to indicate that the packet was discarded. otherwise, the packet will be received normally and bi t 0 set (rcvint) in the interrupt status register. rcv discrd is self clearing. ercv threshold - threshold for ercv interrupt. specified in 64 byte multiples. whenever the number of bytes written in memory for the presently received packet exceeds the ercv threshold, ercv int bit of the interrupt status register is set. bank7 offset name type symbol 0 through 7 external registers ncsout is driven low by the lan91c100fd when a va lid access to the external register range occurs. high byte external r/w register low byte external r/w register cycle ncsout lan91c100fd data bus aen=0 a3=0 a4-15 matches i/o base bank select = 7 driven low. transparently latched on nads rising edge. ignored on writes. tri-stated on reads. bank select = 4,5,6 high ignore cycle. otherwise high normal lan91c100fd cycle.
smsc ds ? lan91c100fd r ev. b page 37 rev. 01-20-06 typical flow of events for transmit s/w driver mac side 1 issue allocate memory for tx - n bytes - the mmu attempts to allocate n bytes of ram. 2 wait for successful completion code - poll until the alloc int bit is set or enable its mask bit and wait for the interrupt. the tx packet number is now at the allocation result register. 3 load transmit data - copy the tx packet number into the packet number register. write the pointer register, then use a block move operation from the upper layer transmit queue into the data register. 4 issue "enqueue packet number to tx fifo" - this command writes the number present in the packet num ber register into the tx fifo. the transmission is now enqueued. no further cpu intervention is needed until a transmit interrupt is generated. 5 the enqueued packet will be transferred to the mac block as a function of txena (ntcr) bit and of the deferral process (1/2 duplex mode only) state. 6 upon transmit completion the first word in memory is written with the status word. the packet number is moved from the tx fifo into the tx completion fifo. interrupt is generated by the tx completion fifo being not empty. 7 service interrupt - read interrupt status register. if it is a transmit interrupt, read the tx done packet number from the fifo ports register. write the packet number into the packet number register. the corresponding status word is now readable from memory. if status word shows successful transmission, issue release packet number command to free up the memory used by this packet. remove packet number from completion fifo by writing tx int acknowledge register.
smsc ds ? lan91c100fd r ev. b page 38 rev. 01-20-06 typical flow of events for receive s/w driver mac side 1 enable reception - by setting the rxen bit. 2 a packet is received with matching address. memory is requested from mmu. a packet number is assigned to it. additional memory is requested if more pages are needed. 3 the internal dma logic generates sequential addresses and writes the receive words into memory. the mmu does the sequential to physical address translation. if overrun, packet is dropped and memory is released. 4 when the end of packet is detected, the status word is placed at the beginning of the receive packet in memory. byte count is placed at the second word. if the crc checks correctly the packet number is written into the rx fifo. the rx fifo, being not empty, causes rcv int (interrupt) to be set. if crc is incorrect the packet memory is released and no interrupt will occur. 5 service interrupt - read the interrupt status register and determine if rcv int is set. the next receive packet is at receive area. (its packet number can be read from the fifo ports register). the software driver can process the packet by accessing the rx area, and can move it out to system memory if desired. when processing is complete the cpu issues the remove and release from top of rx command to have the mmu free up the used memory and packet number.
smsc ds ? lan91c100fd r ev. b page 39 rev. 01-20-06 figure 6 - interrupt service routine isr save bank select & address ptr registers mask smc91c100fd interrupts read interrupt register call tx intr or txempty intr tx intr? get next tx rx intr? ye s no no yes call rxintr alloc intr? no yes write allocated pkt # into packet number reg. write ad ptr reg. & copy data & source address enqueue packet packet available for transmission? ye s n o call allocate eph intr? no ye s call eph intr set "ready for packet" flag return buffers to upper layer disable allocation interrupt mask restore address pointer & bank select registers unmask smc91c100fd interrupts exit isr
smsc ds ? lan91c100fd r ev. b page 40 rev. 01-20-06 rx intr write ad. ptr. reg. & read word 0 from ram destination multicast? read words 2, 3, 4 from ram for address filtering address filtering pass? status word ok? do receive lookahead get copy specs from upper layer okay to copy? copy data per upper layer specs issue "remove and release" command return to isr ye s no ye s no no yes no yes figure 7 - rx intr
smsc ds ? lan91c100fd r ev. b page 41 rev. 01-20-06 write into packet number register tx status ok? tx intr save pkt number register read txdone pkt # from fifo ports reg. immediately issue "release" command acknowledge txintr read tx int again return to isr no ye s read status word from ram update statistics re-enable txena update variables tx int = 0? restore packet number ye s no write address pointer register figure 8 - tx intr
smsc ds ? lan91c100fd r ev. b page 42 rev. 01-20-06 figure 9 - txempty intr (assumes auto release option selected) txempty intr write acknowledge reg. with txempty bit set read txempty & tx intr acknowledge txintr re-enable txena return to isr issue "release" command restore packet number txempty = 0 & txint = 0 (waiting for completion) txempty = x & txint = 1 (transmission failed) txempty = 1 & txint = 0 (everything went through successfully) read pkt. # register & save write address pointer register read status word from ram update statistics update variables
smsc ds ? lan91c100fd r ev. b page 43 rev. 01-20-06 figure 10 - drive send and allocate routines allocate issue "allocate memory" command to mmu read interrupt status register enqueue packet set "ready for packet" flag return copy remaining tx data packet into ram return buffers to upper layer write allocated packet into packet # register write address pointer register copy part of tx data packet into ram write source address into proper location store data buffer pointer clear "ready for packet" flag enable allocation interrupt allocation passed? ye s n o driver send choose bank select register 2 call allocate exit driver send read allocation result register
smsc ds ? lan91c100fd r ev. b page 44 rev. 01-20-06 memory partitioning unlike other controllers, the lan 91c100fd does not require a fixed memory partitioning between transmit and receive resources. the mmu allocates and de-allocates memory upon different events. an additional mechanism allows the cpu to prevent the receive process from starving the transmit memory allocation. memory is always requested by the side that needs to write into it, that is: the cpu for transmit or the mac for receive. the cpu can control the num ber of bytes it requests for transmit but it cannot dete rmine the number of bytes the receive process is going to demand. furt hermore, the receive process requests will be dependent on network traffic, in particular on the arrival of broadcast and multicast packets that might not be for the node, and that are not subject to upper layer software flow control. in order to prevent unwanted traffic from using too much memory, the cp u can program a "memory reserved for transmit" parameter. if the free memory falls below the "m emory reserved for transmit" value, mmu requests from the mac block will fail and the packets will overrun and be ignor ed. whenever enough memory is released, packets can be received again. if the reserved value is too large, the node might lose data which is an abnormal condition. if the value is kept at zero, memory allocation is handled on firs t-come first-served basis for the entire memory capacity. note that with the memory management built into t he lan91c100fd, the cpu can dynamically program this parameter. for instance, when the dr iver does not need to enqueue transmissions, it can allow more memory to be allocated for receive (by reducing t he value of the reserved memory). whenever the driver needs to burst transmissions it can reduce the receive memory allocation. the driver program the parameter as a function of the following variables: 1) free memory (read only register) 2) memory size (read only register) the reserved memory value can be changed on the fly. if the memory reserved for tx value is increased above the free memory, receive packets in progress are still received, but no new pa ckets are accepted until the free memory increases above the memory reserved value. interrupt generation the interrupt strategy for the transmit and receive processes is such that it does not represent t he bottleneck in the transmit and receive queue management between the software driver and the controlle r. for that purpose there is no register reading necessary before the next element in the queue (namely trans mit or receive packet) can be handled by the controller. the transmit and re ceive results are placed in memory. the receive interrupt will be generated w hen the receive queue (fifo of packets) is not empty and receive interrupts are enabled. this allows the interrupt service routine to process many receiv e packets without ex iting, or one at a time if the isr just returns after processing and removing one. there are two types of transmit interrupt strategies: 1) one interrupt per packet. 2) one interrupt per sequence of packets. the strategy is determined by how the transmit in terrupt bits and the auto release bit are used. tx int bit - set whenever the tx completion fifo is not empty. tx empty int bit - set whenever the tx fifo is empty. auto release - when set, successful transmit packets are not written into completion fifo, and their memory is released automatically. 1) one interrupt per packet: enable tx int, set auto re lease=0. the software driver can find the completion result in memory and process the interrupt one packet at a time. depending on the completion code the driver will take different actions. note that the transmit proc ess is working in parallel and other transmissions might be taking place. the lan91c100fd is virtually queuing the packet numbers and their status words. in this case, the transmit interrupt service routine c an find the next packet number to be serviced by reading the tx done packet number at the fifo ports register. this eliminates the need for the driver to keep a list of packet numbers being transmitted. the numbers ar e queued by the lan91c100fd and provided back to the cpu as their transmission completes.
smsc ds ? lan91c100fd r ev. b page 45 rev. 01-20-06 2) one interrupt per sequenc e of packets: enable tx empty int and tx int, set auto release=1. tx empty int is generated only after transmitting the last packet in the fifo. tx int will be set on a fatal transmit error allowing t he cpu to know that the transmit process has stopped and therefore the fifo will not be emptied. this mode has the advantage of a smaller cpu overhead, and faster me mory de-allocation. note that when auto release=1 the cpu is not provided with t he packet numbers that completed successfully. note: the pointer register is shared by any process accessing the lan91c100fd memory. in order to allow processes to be interruptable, the interr upting process is responsible for reading the pointer value before modifying it, saving it, and restoring it before returning from the interrupt. typically there would be three processes using the pointer: 1) transmit loading (sometimes interrupt driven) 2) receive unloading (interrupt driven) 3) transmit status reading (interrupt driven). 1) and 3) also share the usage of t he packet number register. therefore saving and restoring the pnr is also required from interrupt service routines. figure 11 - interrupt generation for transmit, receive, mmu t x f i f o t x c o m p l e t i o n f i f o r x f i f o c s m a / c d l o g i c a l a d d r e s s p a c k e t # m m u p h y s i c a l a d d r e s s r a m cpu address csma address rx packet number rx fifo packet number packet number register pac k # o u t m.s. bit only 'empty' 'not empty' tx done packet number 'not empty' interrupt status register rcv int tx empty int tx int alloc int two options
smsc ds ? lan91c100fd r ev. b page 46 rev. 01-20-06 board setup information the following parameters are obtained from the eeprom as board setup information: ? ethernet individual address ? i/o base address ? 10baset or aui interface ? mii or endec interface ? interrupt line selection all the above mentioned values are r ead from the eeprom upon hardware reset. except for the individual address, the value of the ios switches determines the offset within the eeprom for t hese parameters, in su ch a way that many identical boards can be plugged into the same system by just changing the ios jumpers. in order to support a software utility bas ed installation, even if the eeprom wa s never programmed, the eeprom can be written using the lan91c100fd. one of the ios combination is associated wi th a fixed default value for the key parameters (i/o base, interrupt) that can always be used regardless of the eeprom based value being programmed. this value will be used if a ll ios pins are left open or pulled high. the eeprom is arranged as a 64 x 16 array. the specific target device is the 9346 1024-bit serial eeprom. all eeprom accesses are done in words. all eeprom addresses in the spec are specified as word addresses. register eeprom word address configuration register base register ios value * 4 (ios value * 4) + 1 individual address 20-22 hex if ios2-ios0 = 7, only the individual address is read from the eeprom. currently assigned values are assumed for the other registers. these val ues are default if the eeprom read operation follows hardware reset. the eeprom select bit is used to determine the type of eepr om operation: a) normal or b) general purpose register. a) normal eeprom operation - eeprom select bit = 0 on eeprom read operations (after reset or after se tting reload high) the configuration register and base register are updated with the eeprom values at locati ons defined by the ios2-0 pi ns. the individual address registers are updated with the values stored in the indivi dual address area of the eeprom. on eeprom write operations (after setting the store bi t) the values of the co nfiguration register and base register are written in the eeprom lo cations defined by the ios2-ios0 pins. the three least significant bits of the control register (eeprom selec t, reload and store) are used to control the eeprom. their values are not stored nor loaded from the eeprom. b) general purpose register - eeprom select bit = 1 on eeprom read operations (after setting reload high) the eeprom word address defined by the pointer register 6 least significant bits is r ead into the general purpose register. on eeprom write operations (after setting the store bit) t he value of the general purp ose register is written at the eeprom word address defined by the pointer register 6 least significant bits. reload and store are set by the user to initiate read and write operations respectively. polling the value until read low is used to determine completion. when an eeprom access is in progress the store and reload bits of ctr will
smsc ds ? lan91c100fd r ev. b page 47 rev. 01-20-06 readback as both bits high. no other bits of the lan91c100fd can be read or written until the eeprom operation completes and both bits are clear. this mechanism is also valid for re set initiated reloads. note: if no eeprom is connected to the lan91c100fd, for example for some embedded applications, the eneep pin should be grounded and no accesses to the eeprom will be attemp ted. configuration, ba se, and individual address assume their default values upon hardware reset and the cpu is responsible for programming them for their final value. figure 12 - 64 x 16 serial eeprom map configuration reg. base reg. configuration reg. base reg. configuration reg. base reg. configuration reg. base reg. configuration reg. base reg. configuration reg. base reg. configuration reg. base reg. ia0-1 ia2-3 ia4-5 ios2-0 word address 000 0h 1h 4h 5h 8h 9h ch dh 10h 11h 14h 15h 18h 19h 20h 21h 22h 001 010 011 100 101 110 xxx 16 bits
smsc ds ? lan91c100fd r ev. b page 48 rev. 01-20-06 application considerations the lan91c100fd is envisioned to fit a few different bus types. this section describes the basic guidelines, system level implications and sample configurations for the most re levant bus types. all applic ations are based on buffered architectures with a private sram bus. fast ethernet slave adapter slave non-intelligent board implementi ng 100 mbps and 10 mbps speeds. adapter requires: a) lan91c100fd chip b) four srams (32k x 8 - 25ns) c) serial eeprom (93c46) d) mbps endec and transceiver chip e) mbps mii compliant phy f) some bus specific glue logic target systems: a) vl local bus 32 bit systems b) high-end isa or non-burst eisa machines c) eisa 32 bit slave vl local bus 32 bit systemsvl local bus 32 bit systemsvl local bus 32 bit systems on vl local bus and other 32 bit embedded systems the lan91c100f d is accessed as a 32 bit peripheral in terms of the bus interface. all registers ex cept the data register will be accessed using byte or word instructions. accesses to the data register could use byte, word, or dword instructions. table 3 - vl local bus signal connections vl bus signal lan91c100 signal notes a2-a15 a2-a15 address bus used for i/o space and register decoding, latched by nads rising edge, and transparent on nads low time. m/nio aen qualifies valid i/o decoding - enabled access when low. this signal is latched by nads rising edge and transparent on nads low time. w/nr w/nr direction of access. sampled by the lan91c100fd on first rising clock that has ncycle active. high on writes, low on reads. nrdyrtn nrdyrtn ready return. direct connection to vl bus. nlrdy nsrdy and some logic nsrdy has the appropriate functionality and timing to create the vl nlrdy except that nlrdy behaves like an open drain output most of the time. lclk lclk local bus clock. rising edges used for synchronous bus interface transactions. nreset reset connected via inve rter to the lan91c100fd. nbe0 nbe1 nbe2 nbe3 nbe0 nbe1 nbe2 nbe3 byte enables. latched transparently by nads rising edge. nads nads, ncycle address strobe is connec ted directly to the vl bus. ncycle is
smsc ds ? lan91c100fd r ev. b page 49 rev. 01-20-06 table 3 - vl local bus signal connections vl bus signal lan91c100 signal notes created typically by using nads delayed by one lclk. irqn intr0-intr3 typically uses the interrupt lines on the isa edge connector of vl bus d0-d31 d0-d31 32 bit data bus. the bus byte(s) used to access the device are a function of nbe0-nbe3: nbe0 nbe1 nbe2 nbe3 0 0 0 0 double word access 0 0 1 1 low word access 1 1 0 0 high word access 0 1 1 1 byte 0 access 1 0 1 1 byte 1 access 1 1 0 1 byte 2 access 1 1 1 0 byte 3 access not used = tri-state on reads, ignored on writes. note that nbe2 and nbe3 override the value of a1, which is tied low in this application. nldev nldev nldev is a totem pole output. nldev is active on valid decodes of a15-a4 and aen=0. unused pins vcc nrd nwr gnd a1 nvlbus open ndatacs
smsc ds ? lan91c100fd r ev. b page 50 rev. 01-20-06 figure 13 - lan91c100fd on vl bus w/nr a2-a15 lclk aen reset intr0-intr3 d0-d31 nrdyrtn nbe0-nbe3 nads ncycle nsrdy nldev lan91c100fd w/nr a2-a15 lclk m/nio nreset irqn d0-d31 nrdyrtn nbe0-nbe3 nads nlrdy nldev delay 1 lclk o.c. simulated o.c. vl bus
smsc ds ? lan91c100fd r ev. b page 51 rev. 01-20-06 high-end isa or non-burst eisa machines on isa machines, the lan91c100fd is accessed as a 16 bit per ipheral. no support for xt (8 bit peripheral) is provided. the signal connections are listed in the following table: table 4 - high-end isa or non-burst eisa machines signal connectors isa bus signal lan91c100fd signal notes a1-a15 a1-a15 address bus used for i/o space and register decoding. aen aen qualifies valid i/o decoding - enabled access when low. niord nrd i/o read strobe - asynchronous read accesses. address is valid before leading edge. niowr nwr i/o write strobe - asynchronous write access. address is valid before leading edge. data is latched on trailing edge. iochrdy ardy this signal is negated on leading nrd, nwr if necessary. it is then asserted on clk rising edge after the access condition is satisfied. reset reset a0 nbe0 nsbhe nbe1 irqn intr0-intr3 d0-d15 d0-d15 16 bit data bus. the bus byte(s) used to access the device are a function of nbe0 and nbe1: nbe0 nbe1 d0-d7 d8-d15 0 0 lower upper 0 1 lower not used 1 0 not used upper not used = tri-state on reads, ignored on writes niocs16 nldev buffered nldev is a totem pole output. must be buffered using an open collector driver. nldev is active on valid decodes of a15-a4 and aen=0. unused pins gnd lclk nads vcc nbe2 nbe3 ncycle w/nr nrdyrtn no upper word access.
smsc ds ? lan91c100fd r ev. b page 52 rev. 01-20-06 figure 14 - lan91c100fd on isa bus a1-a15, aen reset nbe2, nbe3 d0-d15 intr0-intr3 nrd nwr nbe0 nbe1 nldev lan91c100fd a1-a15, aen reset vcc d0-d15 nirq niord niowr a0 nsbhe niocs16 o.c. isa bus
smsc ds ? lan91c100fd r ev. b page 53 rev. 01-20-06 eisa 32 bit slaveeisa 32 bit slave on eisa the lan91c100fd is accessed as a 32 bit i/o slave, along with a slave dma type "c" data path option. as an i/o slave, the lan91c100fd uses asynchronous accesses. in creating nrd and nwr inputs, the timing information is externally derived from ncmd edges. given that the access will be at least 1.5 to 2 clocks (more than 180ns at least) there is no need to negate exrdy, simplifying the eisa interface impl ementation. as a dma slave, the lan91c100fd accepts burst transfers and is able to sustain the peak rate of one doubleword every bclk. doubleword alignment is assumed for dma transfers. up to three extra bytes in the beginning and at the end of the transfer should be moved by the cpu using i/o accesses to the data register. the lan91c100fd will sa mple exrdy and postpone dma cycles if the memory cycle solicits wait states. table 5 - eisa 32 bit slave signal connections eisa bus signal lan91c100fd signal notes la2-la15 a2-a15 address bus used for i/o space and register decoding, latched by nads (nstart) trailing edge. m/nio aen aen qualifies valid i/o decoding - enabled access when low. these signals are externally ored. internally the aen pin is latched by nads rising edge and transparent while nads is low. latched w-r combined with ncmd nrd i/o read strobe - asynchronous read accesses. address is valid before its leading edge. must not be active during dma bursts if dma is supported. latched w-r combined with ncmd nwr i/o write strobe - asynchronous write access. address is valid before leading edge . data latched on trailing edge. must not be active during dma bursts if dma is supported. nstart nads address strobe is connected to eisa nstart. resdrv reset nbe0 nbe1 nbe2 nbe3 nbe0 n be1 nbe2 nbe3 byte enables. latched on nads rising edge. irqn intr0-intr3 interrupts used as active high edge triggered d0-d31 d0-d31 32 bit data bus. the bus byte(s) used to access the device are a function of nbe0-nbe3: nbe0 nbe1 nbe2 nbe3 0 0 0 0 double word access 0 0 1 1 low word access 1 1 0 0 high word access 0 1 1 1 byte 0 access 1 0 1 1 byte 1 access 1 1 0 1 byte 2 access 1 1 1 0 byte 3 access not used = tri-state on reads, ignored on writes. note that nbe2 and nbe3 override the value of a1, which is tied low in this application. other combinations of nbe are not supported by the lan91c100fd. software drivers are not anticipated to generate them.
smsc ds ? lan91c100fd r ev. b page 54 rev. 01-20-06 table 5 - eisa 32 bit slave signal connections eisa bus signal lan91c100fd signal notes nex32 nnows (optional additional logic) nldev nldev is a totem pole output. nldev is active on valid decodes of lan91c100fd pins a15-a4, and aen=0. nnows is similar to nldev except that it should go inactive on nstart rising. nnows can be used to request compressed cycles (1.5 bclk long, nrd/nwr will be 1/2 bclk wide). the following signals support slave dma type "c" burst cycles bclk lclk eisa bus clock. data transfer clock for dma bursts. ndak ndatacs dma acknowledge. active during slave dma cycles. used by the lan91c100fd as ndatacs direct access to data path. niorc w/nr indicates the direction and timing of the dma cycles. high during lan91c100fd writes, low during lan91c100fd reads. niowc ncycle indicates slave dma writes. nexrdy nrdyrtn eisa bus signal indicating whether a slave dma cycle will take place on the next bclk rising edge, or should be postponed. nrdyrtn is used as an input in the slave dma mode to bring in exrdy. unused pins vcc nvlbus gnd a1
smsc ds ? lan91c100fd r ev. b page 55 rev. 01-20-06 figure 15 - lan91c100fd on eisa bus a2-a15 reset aen d0-d31 intr0-intr3 nbe0-nbe3 nrd nwr lclk nads nldev lan91c100fd la2-la15 resdrv o.c. eisa bus aen m/nio d0-d31 irqn nbe0-nbe3 latch + gates ncmd nwr bclk nstart nex32
smsc ds ? lan91c100fd r ev. b page 56 rev. 01-20-06 operational description maximum guaranteed ratings* operating tem perature range .................................................................................................... ............ 0 e c to +70 e c storage temper ature range ..................................................................................................... .........-55 e c to + 150 e c lead temperature range (sol dering, 10 seconds ) ................................................................................ ............ +325 e c positive voltage on any pin, with respec t to ground ........................................................................... ...........v cc + 0.3v negative voltage on any pin, with respec t to ground ........................................................................... .................. -0.3v maximum v cc ............................................................................................................................... ............................ +7v *stresses above those listed above coul d cause permanent damage to the device. this is a stress rating only and functional operation of the device at any other condition abov e those indicated in the operation sections of this specification is not implied. note: when powering this device from laboratory or system power supplies, it is important that the absolute maximum ratings not be exceeded or device failure can resul t. some power supplies exhibit voltage spikes on their outputs when the ac power is switched on or off. in addition, voltage tr ansients on the ac power line may appear on the dc output. if this possibility exists, it is suggested that a cl amp circuit be used. dc electrical characteristics (t a = 0 e c - 70 e c, v cc = +5.0 v 10%) parameter symbol min typ max units comments i type input buffer low input level high input level v ili v ihi 2.0 0.8 v v ttl levels is type input buffer low input level high input level schmitt trigger hysteresis v ilis v ihis v hys 2.2 250 0.8 v v mv schmitt trigger schmitt trigger i clk input buffer low input level high input level v ilck v ihck 3.0 0.4 v v input leakage (all i and is buffers except pins with pullups/pulldowns) low input leakage high input leakage i il i ih -10 -10 +10 +10 a a v in = 0 v in = v cc ip type buffers input current i il -150 -75 ma v in = 0 id type buffers input current i ih +75 +150 ma v in = v cc
smsc ds ? lan91c100fd r ev. b page 57 rev. 01-20-06 parameter symbol min typ max units comments o4 type buffer low output level high output level output leakage v ol v oh i ol 2.4 -10 0.4 +10 v v a i ol = 4 ma i oh = -2 ma v in = 0 to v cc i/o4 type buffer low output level high output level output leakage v ol v oh i ol 2.4 -10 0.4 +10 v v a i ol = 4 ma i oh = -2 ma v in = 0 to v cc o12 type buffer low output level high output level output leakage v ol v oh i ol 2.4 -10 0.5 +10 v v a i ol = 12 ma i oh = -6 ma v in = 0 to v cc o16 type buffer low output level high output level output leakage v ol v oh i ol 2.4 -10 0.5 +10 v v a i ol = 16 ma i oh = -8 ma v in = 0 to v cc od16 type buffer low output level output leakage v ol i ol -10 0.5 +10 v a i ol = 16 ma v in = 0 to v cc o24 type buffer low output level high output level output leakage v ol v oh i ol 2.4 -10 0.5 +10 v v a i ol = 24 ma i oh = -12 ma v in = 0 to v cc i/o24 type buffer low output level high output level output leakage v ol v oh i ol 2.4 -10 0.5 +10 v v a i ol = 24 ma i oh = -12 ma v in = 0 to v cc supply current active supply current standby i cc i csby 60 8 95 ma ma all outputs open
smsc ds ? lan91c100fd r ev. b page 58 rev. 01-20-06 capacitance t a = 25 e c; fc = 1mhz; v cc = 5v limits parameter symbol min typ max unit test condition clock input capacitance c in 20 pf all pins except pin under test tied to ac ground input capacitance c in 10 pf output capacitance c out 20 pf capacitive load on outputs nardy, d0-d31 (non vlbus) 240 pf d0-d31 in vlbus 45 pf all other outputs 45 pf
smsc ds ? lan91c100fd r ev. b page 59 rev. 01-20-06 timing diagrams figure 16 - asynchronous cycle - nads=0 parameter min typ max units t1 a1-a15, aen, nbe0-nbe3 valid and nads low setup to nrd, nwr active 25 ns t2 a1-a15, aen, nbe0-nbe3 hold after nrd, nwr inactive (assuming nads tied low) 20 ns t3 nrd low to valid data 40 ns t4 nrd high to data floating 30 ns t5 data setup to nwr inactive 30 ns t5a data hold after nwr inactive 5 ns figure 17 - asynchronous cycle - using nads parameter min typ max units t1 a1-a15, aen, nbe0-nbe3 valid and nads low setup to nrd, nwr active 25 ns t3 nrd low to valid data 40 ns t4 nrd high to data floating 30 ns t5 data setup to nwr inactive 30 ns t5a data hold after nwr inactive 5 ns t8 a1-a15, aen, nbe0-nbe3 setup to nads rising 10 ns t9 a1-a15, aen, nbe0-nbe3 hold after nads rising 15 ns t5 t2 t3 t4 t1 t5a a1-15, aen, nbe0-nbe3 valid d0-d31 valid address nads read data nrd,nwr write data t8 t9 t5 t3 t4 t1 t5a a1-a15, aen, nbe0-nbe3 valid d0-d31 valid address nads read data nrd, nwr write data
smsc ds ? lan91c100fd r ev. b page 60 rev. 01-20-06 figure 18 - asynchronous cycle - nads=0 (ndatacs used to select data register; must be 32 bit access) parameter min typ max units t1 a1-a15, aen, nbe0-nbe3 valid and nads low setup to nrd, nwr active 25 ns t2 a1-a15, aen, nbe0-nbe3 hold after nrd, nwr inactive (assuming nads tied low) 20 ns t3 nrd low to valid data 40 ns t4 nrd high to data floating 30 ns t5 data setup to nwr inactive 30 ns t5a data hold after nwr inactive 5 ns t5 t2 t3 t4 t1 t5a d0-d31 valid ndatacs nads read data nrd, nwr wri te data
smsc ds ? lan91c100fd r ev. b page 61 rev. 01-20-06 figure 19 - burst write cycles - nvlbus=1 parameter min typ max units t12 ndatacs setup to either ncycle or w/nr falling 60 ns t13 ndatacs hold after either ncycle or w/nr rising 30 ns t14 nrdyrtn setup to lclk falling 15 ns t15 nrdyrtn hold after lclk falling 2 ns t17 ncycle high and w/nr high overlap 50 ns t18 data setup to lclk rising (write) 13 ns t20 data hold from lclk rising (write) 5 ns figure 20 - burst read cycles - nvlbus=1 parameter min typ max units t12 ndatacs setup to either ncycle or w/nr falling 60 ns t13 ndatacs hold after either ncycle or w/nr rising 30 ns t14 nrdyrtn setup to lclk falling 15 ns t15 nrdyrtn hold after lclk falling 2 ns t17 ncycle high and w/nr high overlap 50 ns t19 data delay from lclk rising (read) 5* 38** ns note *: (holdt.) note **: (setupt.) t12 t18 t20 t14 t15 t13 t17 t17 a b c lclk ndatacs w/nr ncycle write data nrdyrtn t12 t14 t15 t13 t17 t19 t17 c ab lclk ndatacs w/nr read data nrdyrtn ncycle
smsc ds ? lan91c100fd r ev. b page 62 rev. 01-20-06 figure 21 - address latching for all modes parameter min typ max units t8 a1-a15, aen, nbe0-nbe3 setup to nads rising 10 ns t9 a1-a15, aen, nbe0-nbe3 hold after nads rising 15 ns t25 a4-a15, aen to nldev delay 20 ns figu re 22 - synchronous write cycle - nvlbus=0 parameter min typ max units t8 a1-a15, aen, nbe0-nbe3 setup to nads rising 10 ns t9 a1-a15, aen, nbe0-nbe3 hold after nads rising 15 ns t10 ncycle setup to lclk rising 7 ns t11 ncycle hold after lclk rising (non-burst mode) 3 ns t16 w/nr setup to ncycle active 30 ns t17a w/nr hold after lclk rising with nlrdy active 5 ns t18 data setup to lclk rising (write) 13 ns t20 data hold from lclk rising (write) 5 ns t21 nlrdy delay from lclk rising 10 ns t8 t9 t25 a1-a15, aen, nbe0-nbe3 nads address nldev t18 t20 t10 t11 t17a t9 t8 t16 t21 t21 d0-d31 valid a1-a15, aen, nbe0-nbe3 lclk w/nr address nads ncycle write data nsrdy ndatacs
smsc ds ? lan91c100fd r ev. b page 63 rev. 01-20-06 figure 23 - synchronous read cycle - nvlbus=0 parameter min typ max units t8 a1-a15, aen, nbe0-nbe3 setup to nads rising 10 ns t9 a1-a15, aen, nbe0-nbe3 hold after nads rising 15 ns t10 ncycle setup to lclk rising 7 ns t11 ncycle hold after lclk rising (non-burst mode) 3 ns t16 w/nr setup to ncycle active 30 ns t20 data hold from lclk rising (read) 5 ns t21 nlrdy delay from lclk rising 10 ns t23 nrdyrtn setup to lclk rising 7 ns t24 nrdyrtn hold after lclk rising 3 ns t23 t24 t10 t11 t9 t8 t16 t21 t21 d0-d31 a 1-a15, aen, nbe0-nbe3 lclk w/nr a ddres nads ncycl read nsrd rdyrt ndatac
smsc ds ? lan91c100fd r ev. b page 64 rev. 01-20-06 figure 24 - sram interface parameter min typ max units t34 write ? ra2-ra16 setup to nrwe0-nrwe3 falling 0 ns t35 write ? ra2-ra16 hold after nrwe0-nrwe3 rising 0 ns t36 write ? rd0-rd31 setup to nrwe0-nrwe3 rising 12 ns t37 write ? rd0-rd31 hold after nrwe0-nrwe3 rising 0 ns t39 write ? nrwe0-nrwe3 pulse width 15 ns t38 read ? ra2-ra16 valid to rd0-rd31 valid 25 ns t51 read ? rd0-rd31 hold after ra2-ra16 change 12 ns t37 t36 t39 t39 t51 t38 t35 t34 read cycle write cycle ra2-ra16 nrwe0-nrwe3 nroe rd0-rd31 t38 t51 t38 t51 t38 t51 t38 multiple read cycles ra2-ra16 nrwe0-nrwe3 nroe rd0-rd31 t37 t36 t39 t39 t35 t34 t51 t38 read cycle write cycle ra2-ra16 nrwe0-nrwe3 nroe rd0-rd31
smsc ds ? lan91c100fd r ev. b page 65 rev. 01-20-06 figure 25 - endec interface - 10 mbps parameter min typ max units t30 txd, txen delay from txc rising 0 40 ns t31 rxd setup to rxc rising 10 ns t32 rxd hold after rxc rising 30 ns notes: 1. crs input might be asynchronous to rxc. 2. rxc starts after crs goes active. rxc stops after crs goes inactive. 3. col is an asynchronous input. figure 26 - mii interface parameter min typ max units t27 txd0-txd3, txen100 delay from tx25 rising 0 15 ns t28 rxd0-rxd3, rx_dv, rx_er setup to rx25 rising 10 ns t29 rxd0-rxd3, rx_dv, rx_er hold after rx25 rising 10 ns t31 t30 t30 t30 t32 txc txen txd rxd rxc crs t28 t28 t28 t27 t27 t29 t29 txd0-txd3 txen100 rxd0-rxd3 rx25 rx_dv rx_er
smsc ds ? lan91c100fd r ev. b page 66 rev. 01-20-06 figure 27 - 208 pin pqfp package outlines see detail 'a' 52 d d1 3 156 105 104 3 157 detail 'a' r1 r2 4 l l1 5 ee1 208 1 1 0.10 c h a1 a a2 53 e 2 w d1/4 e1/4 0 notes: coplanarity is 0.100mm maximum. tolerance on the position of the leads is 0.08mm maximum. package body dimensions d1 and e1 do not include the mold protrusion. maximum mold protrusion is 0.25mm. dimensions for foot length l when measured at the centerline of the leads are given in the table. dimension for foot length l when measured at the gauge plane 0.25mm above the seating plane, is 0.6mm. details of pin 1 identifier are optional but must be located within the zone indicated. 6. controlling dimension: millimeter 1 2 3 4 5 dim a a1 a2 d d1 e e1 h l l1 e 0 w r1 r2 min 0.05 3.17 30.35 27.90 30.35 27.90 0.09 0.35 nom 30.60 28.00 30.60 28.00 0.5 1.30 max 4.07 0.5 3.67 30.85 28.10 30.85 28.10 0.23 0.65 0 0.10 0.20 0.30 0.50 bsc 7 0.30
smsc ds ? lan91c100fd r ev. b page 67 rev. 01-20-06 figure 28 - 208 pin tqfp package outlines 1 2 3 4 5 nom 30.00 15.00 28.00 30.00 15.00 28.00 0.60 1.00 0.50 bsc dim a a1 a2 d d/2 d1 e e/2 e1 h l l1 e 0 w r1 r2 ccc ccc remark overall package height standoff body thickness x span 1/2 x span measure from centerline x body size y span 1/2 y span measure from centerline y body size lead frame thickness lead foot length from centerline lead length lead pitch lead foot angle lead width lead shoulder radius lead foot radius coplanarity (assemblers) coplanarity (test house) min 0.05 1.35 29.80 14.90 27.90 29.80 14.90 27.90 0.09 0.45 0 0.17 0.08 0.08 max 1.60 0.15 1.45 30.20 15.10 28.10 30.20 15.10 28.10 0.23 0.75 7 0.27 0.20 0.0762 0.08 notes: controlling unit: millimeter. tolerance on the position of the leads is 0.04mm maximum. package body dimensions d1 and e1 do not include the mold protrusion. maximum mold protrusion is 0.25mm. dimension for foot length l measured at the gauge plane 0.25mm above the seating plane, is 0.78-1.08mm. details of pin 1 identifier are optional but must be located within the zone indicated.

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